Unified Coverage Report :: Module :: prim_lc_sync

Module : prim_lc_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_clkmgr_byp.u_en_sync	100.00	100.00					100.00
tb.dut.u_clkmgr_byp.u_lc_byp_req	100.00	100.00					100.00

---

Module Instance : tb.dut.u_clkmgr_byp.u_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_clkmgr_byp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_clkmgr_byp.u_lc_byp_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_clkmgr_byp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=1,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_clkmgr_byp.u_en_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=2,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_clkmgr_byp.u_lc_byp_req

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	2	2

---

Assert Coverage for Module : prim_lc_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1540	1540	0	0
OutputsKnown_A	104398492	100163224	0	0
gen_flops.OutputDelay_A	104398492	100150702	0	4620

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1540	1540	0	0
T1	2	2	0	0
T2	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T14	2	2	0	0
T15	2	2	0	0
T16	2	2	0	0
T17	2	2	0	0
T18	2	2	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104398492	100163224	0	0
T1	467506	467228	0	0
T2	37788	37678	0	0
T4	130498	130174	0	0
T5	1304	1242	0	0
T6	4558	4484	0	0
T14	2094	2030	0	0
T15	2552	2450	0	0
T16	3478	2998	0	0
T17	2008	1810	0	0
T18	49608	49472	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104398492	100150702	0	4620
T1	467506	467222	0	6
T2	37788	37672	0	6
T4	130498	130168	0	6
T5	1304	1236	0	6
T6	4558	4478	0	6
T14	2094	2024	0	6
T15	2552	2444	0	6
T16	3478	2992	0	6
T17	2008	1804	0	6
T18	49608	49466	0	6

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_en_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_en_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	770	770	0	0
OutputsKnown_A	52199246	50081612	0	0
gen_flops.OutputDelay_A	52199246	50075351	0	2310

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	770	770	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52199246	50081612	0	0
T1	233753	233614	0	0
T2	18894	18839	0	0
T4	65249	65087	0	0
T5	652	621	0	0
T6	2279	2242	0	0
T14	1047	1015	0	0
T15	1276	1225	0	0
T16	1739	1499	0	0
T17	1004	905	0	0
T18	24804	24736	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52199246	50075351	0	2310
T1	233753	233611	0	3
T2	18894	18836	0	3
T4	65249	65084	0	3
T5	652	618	0	3
T6	2279	2239	0	3
T14	1047	1012	0	3
T15	1276	1222	0	3
T16	1739	1496	0	3
T17	1004	902	0	3
T18	24804	24733	0	3

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_lc_byp_req

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	2	2

---

Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_lc_byp_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	770	770	0	0
OutputsKnown_A	52199246	50081612	0	0
gen_flops.OutputDelay_A	52199246	50075351	0	2310

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	770	770	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52199246	50081612	0	0
T1	233753	233614	0	0
T2	18894	18839	0	0
T4	65249	65087	0	0
T5	652	621	0	0
T6	2279	2242	0	0
T14	1047	1015	0	0
T15	1276	1225	0	0
T16	1739	1499	0	0
T17	1004	905	0	0
T18	24804	24736	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52199246	50075351	0	2310
T1	233753	233611	0	3
T2	18894	18836	0	3
T4	65249	65084	0	3
T5	652	618	0	3
T6	2279	2239	0	3
T14	1047	1012	0	3
T15	1276	1222	0	3
T16	1739	1496	0	3
T17	1004	902	0	3
T18	24804	24733	0	3