Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	53137539	1219482	0	0
clk_enables_rd_A	53137539	11241	0	0
clk_hints_rd_A	53137539	10024	0	0
extclk_ctrl_rd_A	53137539	14407	0	0
extclk_ctrl_regwen_rd_A	53137539	9508	0	0
jitter_enable_rd_A	53137539	15682	0	0
jitter_regwen_rd_A	53137539	9776	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53137539	1219482	0	0
T8	253722	87013	0	0
T9	18606	0	0	0
T10	26151	0	0	0
T33	0	89031	0	0
T35	1573	0	0	0
T39	0	104386	0	0
T40	0	169562	0	0
T69	0	131891	0	0
T70	0	80099	0	0
T71	0	71333	0	0
T72	0	19471	0	0
T73	0	86075	0	0
T74	0	97798	0	0
T75	1079	0	0	0
T76	699	0	0	0
T77	1304	0	0	0
T78	1719	0	0	0
T79	2346	0	0	0
T80	1088	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53137539	11241	0	0
T11	201508	0	0	0
T24	0	15	0	0
T26	116903	0	0	0
T31	1823	0	0	0
T37	2019	2	0	0
T116	1072	0	0	0
T117	2356	0	0	0
T118	3760	0	0	0
T135	0	6	0	0
T136	0	1	0	0
T137	0	12	0	0
T138	0	5	0	0
T139	0	8	0	0
T140	0	11	0	0
T141	0	8	0	0
T142	0	3	0	0
T143	1556	0	0	0
T144	2227	0	0	0
T145	2785	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53137539	10024	0	0
T11	201508	0	0	0
T24	0	21	0	0
T26	116903	0	0	0
T31	1823	0	0	0
T37	2019	6	0	0
T116	1072	0	0	0
T117	2356	0	0	0
T118	3760	0	0	0
T135	0	6	0	0
T136	0	3	0	0
T137	0	20	0	0
T138	0	5	0	0
T139	0	8	0	0
T140	0	3	0	0
T141	0	6	0	0
T143	1556	0	0	0
T144	2227	0	0	0
T145	2785	0	0	0
T146	0	2	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53137539	14407	0	0
T7	55584	0	0	0
T8	253722	0	0	0
T9	18606	0	0	0
T10	26151	0	0	0
T24	0	139	0	0
T34	1700	0	0	0
T38	1994	32	0	0
T41	1570	0	0	0
T75	1079	0	0	0
T80	0	12	0	0
T91	2933	0	0	0
T103	0	54	0	0
T104	1538	0	0	0
T118	0	37	0	0
T144	0	17	0	0
T147	0	25	0	0
T148	0	28	0	0
T149	0	54	0	0
T150	0	72	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53137539	9508	0	0
T103	12981	31	0	0
T136	2336	0	0	0
T151	0	78	0	0
T152	0	68	0	0
T153	0	7	0	0
T154	0	23	0	0
T155	0	56	0	0
T156	0	2	0	0
T157	0	10	0	0
T158	0	10	0	0
T159	0	53	0	0
T160	1539	0	0	0
T161	26550	0	0	0
T162	2541	0	0	0
T163	1170	0	0	0
T164	55249	0	0	0
T165	1919	0	0	0
T166	2714	0	0	0
T167	2409	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53137539	15682	0	0
T11	201508	0	0	0
T24	0	429	0	0
T26	116903	0	0	0
T31	1823	0	0	0
T37	2019	81	0	0
T116	1072	0	0	0
T117	2356	0	0	0
T118	3760	0	0	0
T135	0	115	0	0
T136	0	109	0	0
T137	0	376	0	0
T138	0	110	0	0
T139	0	31	0	0
T140	0	122	0	0
T143	1556	0	0	0
T144	2227	0	0	0
T145	2785	0	0	0
T146	0	121	0	0
T168	0	107	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53137539	9776	0	0
T33	0	3315	0	0
T57	0	105	0	0
T72	651198	882	0	0
T84	0	56	0	0
T100	0	29	0	0
T105	0	65	0	0
T107	0	11	0	0
T169	0	1251	0	0
T170	0	2398	0	0
T171	0	10	0	0
T172	2208	0	0	0
T173	3653	0	0	0
T174	55674	0	0	0
T175	733	0	0	0
T176	1640	0	0	0
T177	1598	0	0	0
T178	990	0	0	0
T179	21597	0	0	0
T180	6335	0	0	0