Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	156597738	398	0	0
StatusRise_A	156597738	398	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156597738	398	0	0
T3	402267	0	0	0
T14	3141	10	0	0
T15	3828	0	0	0
T16	5217	0	0	0
T17	3012	0	0	0
T18	74412	0	0	0
T19	3123	0	0	0
T20	8355	0	0	0
T35	0	15	0	0
T36	0	9	0	0
T38	5982	0	0	0
T48	0	5	0	0
T51	0	11	0	0
T54	0	5	0	0
T104	4614	0	0	0
T181	0	10	0	0
T182	0	7	0	0
T183	0	4	0	0
T184	0	9	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	156597738	398	0	0
T3	402267	0	0	0
T14	3141	10	0	0
T15	3828	0	0	0
T16	5217	0	0	0
T17	3012	0	0	0
T18	74412	0	0	0
T19	3123	0	0	0
T20	8355	0	0	0
T35	0	15	0	0
T36	0	9	0	0
T38	5982	0	0	0
T48	0	5	0	0
T51	0	11	0	0
T54	0	5	0	0
T104	4614	0	0	0
T181	0	10	0	0
T182	0	7	0	0
T183	0	4	0	0
T184	0	9	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	52199246	132	0	0
StatusRise_A	52199246	132	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52199246	132	0	0
T3	134089	0	0	0
T14	1047	3	0	0
T15	1276	0	0	0
T16	1739	0	0	0
T17	1004	0	0	0
T18	24804	0	0	0
T19	1041	0	0	0
T20	2785	0	0	0
T35	0	4	0	0
T36	0	2	0	0
T38	1994	0	0	0
T48	0	1	0	0
T51	0	4	0	0
T54	0	2	0	0
T104	1538	0	0	0
T181	0	4	0	0
T182	0	3	0	0
T183	0	1	0	0
T184	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52199246	132	0	0
T3	134089	0	0	0
T14	1047	3	0	0
T15	1276	0	0	0
T16	1739	0	0	0
T17	1004	0	0	0
T18	24804	0	0	0
T19	1041	0	0	0
T20	2785	0	0	0
T35	0	4	0	0
T36	0	2	0	0
T38	1994	0	0	0
T48	0	1	0	0
T51	0	4	0	0
T54	0	2	0	0
T104	1538	0	0	0
T181	0	4	0	0
T182	0	3	0	0
T183	0	1	0	0
T184	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	52199246	132	0	0
StatusRise_A	52199246	132	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52199246	132	0	0
T3	134089	0	0	0
T14	1047	4	0	0
T15	1276	0	0	0
T16	1739	0	0	0
T17	1004	0	0	0
T18	24804	0	0	0
T19	1041	0	0	0
T20	2785	0	0	0
T35	0	6	0	0
T36	0	3	0	0
T38	1994	0	0	0
T48	0	1	0	0
T51	0	4	0	0
T54	0	1	0	0
T104	1538	0	0	0
T181	0	3	0	0
T182	0	2	0	0
T183	0	1	0	0
T184	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52199246	132	0	0
T3	134089	0	0	0
T14	1047	4	0	0
T15	1276	0	0	0
T16	1739	0	0	0
T17	1004	0	0	0
T18	24804	0	0	0
T19	1041	0	0	0
T20	2785	0	0	0
T35	0	6	0	0
T36	0	3	0	0
T38	1994	0	0	0
T48	0	1	0	0
T51	0	4	0	0
T54	0	1	0	0
T104	1538	0	0	0
T181	0	3	0	0
T182	0	2	0	0
T183	0	1	0	0
T184	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	52199246	134	0	0
StatusRise_A	52199246	134	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52199246	134	0	0
T3	134089	0	0	0
T14	1047	3	0	0
T15	1276	0	0	0
T16	1739	0	0	0
T17	1004	0	0	0
T18	24804	0	0	0
T19	1041	0	0	0
T20	2785	0	0	0
T35	0	5	0	0
T36	0	4	0	0
T38	1994	0	0	0
T48	0	3	0	0
T51	0	3	0	0
T54	0	2	0	0
T104	1538	0	0	0
T181	0	3	0	0
T182	0	2	0	0
T183	0	2	0	0
T184	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52199246	134	0	0
T3	134089	0	0	0
T14	1047	3	0	0
T15	1276	0	0	0
T16	1739	0	0	0
T17	1004	0	0	0
T18	24804	0	0	0
T19	1041	0	0	0
T20	2785	0	0	0
T35	0	5	0	0
T36	0	4	0	0
T38	1994	0	0	0
T48	0	3	0	0
T51	0	3	0	0
T54	0	2	0	0
T104	1538	0	0	0
T181	0	3	0	0
T182	0	2	0	0
T183	0	2	0	0
T184	0	3	0	0