Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T8,T10
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	26822	0	0
CgEnOn_A	2147483647	18674	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	26822	0	0
T1	509946	3	0	0
T2	123567	3	0	0
T3	1316462	0	0	0
T4	146752	3	0	0
T5	10738	3	0	0
T6	19006	3	0	0
T14	44848	38	0	0
T15	58010	3	0	0
T16	18572	3	0	0
T17	22938	3	0	0
T18	464428	3	0	0
T19	40757	1	0	0
T20	48009	10	0	0
T35	0	34	0	0
T36	0	15	0	0
T38	27822	0	0	0
T48	0	5	0	0
T51	0	20	0	0
T54	0	5	0	0
T104	13369	0	0	0
T181	0	15	0	0
T182	0	10	0	0
T183	0	5	0	0
T184	0	20	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	18674	0	0
T3	1645544	0	0	0
T8	0	220	0	0
T10	0	23	0	0
T14	44848	35	0	0
T15	58010	0	0	0
T16	18572	0	0	0
T17	22938	0	0	0
T18	464428	0	0	0
T19	50892	4	0	0
T20	59964	10	0	0
T34	0	1	0	0
T35	0	52	0	0
T36	0	15	0	0
T37	0	4	0	0
T38	34948	0	0	0
T41	0	39	0	0
T48	0	5	0	0
T51	0	20	0	0
T54	0	5	0	0
T78	0	5	0	0
T104	16690	0	0	0
T181	0	15	0	0
T182	0	10	0	0
T183	0	5	0	0
T184	0	20	0	0
T185	0	3	0	0
T186	0	45	0	0
T187	0	39	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T8,T10
1	0	Unreachable
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	101364988	138	0	0
CgEnOn_A	101364988	138	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101364988	138	0	0
T3	73107	0	0	0
T14	1982	4	0	0
T15	2694	0	0	0
T16	782	0	0	0
T17	988	0	0	0
T18	18490	0	0	0
T19	2212	0	0	0
T20	2621	0	0	0
T35	0	6	0	0
T36	0	3	0	0
T38	1714	0	0	0
T48	0	1	0	0
T51	0	4	0	0
T54	0	1	0	0
T104	723	0	0	0
T181	0	3	0	0
T182	0	2	0	0
T183	0	1	0	0
T184	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101364988	138	0	0
T3	73107	0	0	0
T14	1982	4	0	0
T15	2694	0	0	0
T16	782	0	0	0
T17	988	0	0	0
T18	18490	0	0	0
T19	2212	0	0	0
T20	2621	0	0	0
T35	0	6	0	0
T36	0	3	0	0
T38	1714	0	0	0
T48	0	1	0	0
T51	0	4	0	0
T54	0	1	0	0
T104	723	0	0	0
T181	0	3	0	0
T182	0	2	0	0
T183	0	1	0	0
T184	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T8,T10
1	0	Unreachable
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	50682147	138	0	0
CgEnOn_A	50682147	138	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50682147	138	0	0
T3	36553	0	0	0
T14	991	4	0	0
T15	1347	0	0	0
T16	391	0	0	0
T17	494	0	0	0
T18	9245	0	0	0
T19	1106	0	0	0
T20	1311	0	0	0
T35	0	6	0	0
T36	0	3	0	0
T38	856	0	0	0
T48	0	1	0	0
T51	0	4	0	0
T54	0	1	0	0
T104	362	0	0	0
T181	0	3	0	0
T182	0	2	0	0
T183	0	1	0	0
T184	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50682147	138	0	0
T3	36553	0	0	0
T14	991	4	0	0
T15	1347	0	0	0
T16	391	0	0	0
T17	494	0	0	0
T18	9245	0	0	0
T19	1106	0	0	0
T20	1311	0	0	0
T35	0	6	0	0
T36	0	3	0	0
T38	856	0	0	0
T48	0	1	0	0
T51	0	4	0	0
T54	0	1	0	0
T104	362	0	0	0
T181	0	3	0	0
T182	0	2	0	0
T183	0	1	0	0
T184	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T8,T10
1	0	Unreachable
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	50682147	138	0	0
CgEnOn_A	50682147	138	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50682147	138	0	0
T3	36553	0	0	0
T14	991	4	0	0
T15	1347	0	0	0
T16	391	0	0	0
T17	494	0	0	0
T18	9245	0	0	0
T19	1106	0	0	0
T20	1311	0	0	0
T35	0	6	0	0
T36	0	3	0	0
T38	856	0	0	0
T48	0	1	0	0
T51	0	4	0	0
T54	0	1	0	0
T104	362	0	0	0
T181	0	3	0	0
T182	0	2	0	0
T183	0	1	0	0
T184	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50682147	138	0	0
T3	36553	0	0	0
T14	991	4	0	0
T15	1347	0	0	0
T16	391	0	0	0
T17	494	0	0	0
T18	9245	0	0	0
T19	1106	0	0	0
T20	1311	0	0	0
T35	0	6	0	0
T36	0	3	0	0
T38	856	0	0	0
T48	0	1	0	0
T51	0	4	0	0
T54	0	1	0	0
T104	362	0	0	0
T181	0	3	0	0
T182	0	2	0	0
T183	0	1	0	0
T184	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T8,T10
1	0	Unreachable
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	50682147	138	0	0
CgEnOn_A	50682147	138	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50682147	138	0	0
T3	36553	0	0	0
T14	991	4	0	0
T15	1347	0	0	0
T16	391	0	0	0
T17	494	0	0	0
T18	9245	0	0	0
T19	1106	0	0	0
T20	1311	0	0	0
T35	0	6	0	0
T36	0	3	0	0
T38	856	0	0	0
T48	0	1	0	0
T51	0	4	0	0
T54	0	1	0	0
T104	362	0	0	0
T181	0	3	0	0
T182	0	2	0	0
T183	0	1	0	0
T184	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50682147	138	0	0
T3	36553	0	0	0
T14	991	4	0	0
T15	1347	0	0	0
T16	391	0	0	0
T17	494	0	0	0
T18	9245	0	0	0
T19	1106	0	0	0
T20	1311	0	0	0
T35	0	6	0	0
T36	0	3	0	0
T38	856	0	0	0
T48	0	1	0	0
T51	0	4	0	0
T54	0	1	0	0
T104	362	0	0	0
T181	0	3	0	0
T182	0	2	0	0
T183	0	1	0	0
T184	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T8,T10
1	0	Unreachable
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	204087749	138	0	0
CgEnOn_A	204087749	133	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	204087749	138	0	0
T3	146279	0	0	0
T14	4016	4	0	0
T15	5107	0	0	0
T16	1670	0	0	0
T17	2053	0	0	0
T18	37073	0	0	0
T19	4545	0	0	0
T20	5349	0	0	0
T35	0	6	0	0
T36	0	3	0	0
T38	3037	0	0	0
T48	0	1	0	0
T51	0	4	0	0
T54	0	1	0	0
T104	1491	0	0	0
T181	0	3	0	0
T182	0	2	0	0
T183	0	1	0	0
T184	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	204087749	133	0	0
T3	146279	0	0	0
T14	4016	4	0	0
T15	5107	0	0	0
T16	1670	0	0	0
T17	2053	0	0	0
T18	37073	0	0	0
T19	4545	0	0	0
T20	5349	0	0	0
T35	0	6	0	0
T36	0	3	0	0
T38	3037	0	0	0
T48	0	1	0	0
T51	0	4	0	0
T54	0	1	0	0
T104	1491	0	0	0
T181	0	3	0	0
T182	0	2	0	0
T183	0	1	0	0
T184	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T8,T10
1	0	Unreachable
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	216807734	132	0	0
CgEnOn_A	216807734	132	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216807734	132	0	0
T3	152379	0	0	0
T14	4111	3	0	0
T15	5319	0	0	0
T16	1739	0	0	0
T17	2138	0	0	0
T18	44621	0	0	0
T19	4735	0	0	0
T20	5572	0	0	0
T35	0	4	0	0
T36	0	2	0	0
T38	3164	0	0	0
T48	0	1	0	0
T51	0	4	0	0
T54	0	2	0	0
T104	1554	0	0	0
T181	0	4	0	0
T182	0	3	0	0
T183	0	1	0	0
T184	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216807734	132	0	0
T3	152379	0	0	0
T14	4111	3	0	0
T15	5319	0	0	0
T16	1739	0	0	0
T17	2138	0	0	0
T18	44621	0	0	0
T19	4735	0	0	0
T20	5572	0	0	0
T35	0	4	0	0
T36	0	2	0	0
T38	3164	0	0	0
T48	0	1	0	0
T51	0	4	0	0
T54	0	2	0	0
T104	1554	0	0	0
T181	0	4	0	0
T182	0	3	0	0
T183	0	1	0	0
T184	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T8,T10
1	0	Unreachable
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	216807734	132	0	0
CgEnOn_A	216807734	132	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216807734	132	0	0
T3	152379	0	0	0
T14	4111	3	0	0
T15	5319	0	0	0
T16	1739	0	0	0
T17	2138	0	0	0
T18	44621	0	0	0
T19	4735	0	0	0
T20	5572	0	0	0
T35	0	4	0	0
T36	0	2	0	0
T38	3164	0	0	0
T48	0	1	0	0
T51	0	4	0	0
T54	0	2	0	0
T104	1554	0	0	0
T181	0	4	0	0
T182	0	3	0	0
T183	0	1	0	0
T184	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216807734	132	0	0
T3	152379	0	0	0
T14	4111	3	0	0
T15	5319	0	0	0
T16	1739	0	0	0
T17	2138	0	0	0
T18	44621	0	0	0
T19	4735	0	0	0
T20	5572	0	0	0
T35	0	4	0	0
T36	0	2	0	0
T38	3164	0	0	0
T48	0	1	0	0
T51	0	4	0	0
T54	0	2	0	0
T104	1554	0	0	0
T181	0	4	0	0
T182	0	3	0	0
T183	0	1	0	0
T184	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T8,T10
1	0	Unreachable
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	104045403	136	0	0
CgEnOn_A	104045403	135	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104045403	136	0	0
T3	73143	0	0	0
T14	2111	3	0	0
T15	2553	0	0	0
T16	835	0	0	0
T17	1026	0	0	0
T18	24298	0	0	0
T19	2272	0	0	0
T20	2674	0	0	0
T35	0	5	0	0
T36	0	4	0	0
T38	1519	0	0	0
T48	0	3	0	0
T51	0	3	0	0
T54	0	2	0	0
T104	745	0	0	0
T181	0	3	0	0
T182	0	2	0	0
T183	0	2	0	0
T184	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104045403	135	0	0
T3	73143	0	0	0
T14	2111	3	0	0
T15	2553	0	0	0
T16	835	0	0	0
T17	1026	0	0	0
T18	24298	0	0	0
T19	2272	0	0	0
T20	2674	0	0	0
T35	0	5	0	0
T36	0	4	0	0
T38	1519	0	0	0
T48	0	3	0	0
T51	0	3	0	0
T54	0	2	0	0
T104	745	0	0	0
T181	0	3	0	0
T182	0	2	0	0
T183	0	2	0	0
T184	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T35,T36
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	50682147	4370	0	0
CgEnOn_A	50682147	2337	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50682147	4370	0	0
T1	56649	1	0	0
T2	13707	1	0	0
T4	16292	1	0	0
T5	1173	1	0	0
T6	2283	1	0	0
T14	991	5	0	0
T15	1347	1	0	0
T16	391	1	0	0
T17	494	1	0	0
T18	9245	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50682147	2337	0	0
T3	36553	0	0	0
T8	0	58	0	0
T10	0	7	0	0
T14	991	4	0	0
T15	1347	0	0	0
T16	391	0	0	0
T17	494	0	0	0
T18	9245	0	0	0
T19	1106	1	0	0
T20	1311	0	0	0
T35	0	6	0	0
T37	0	1	0	0
T38	856	0	0	0
T41	0	12	0	0
T104	362	0	0	0
T185	0	1	0	0
T186	0	14	0	0
T187	0	12	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T35,T36
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	101364988	4397	0	0
CgEnOn_A	101364988	2364	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101364988	4397	0	0
T1	113298	1	0	0
T2	27414	1	0	0
T4	32585	1	0	0
T5	2346	1	0	0
T6	4569	1	0	0
T14	1982	5	0	0
T15	2694	1	0	0
T16	782	1	0	0
T17	988	1	0	0
T18	18490	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101364988	2364	0	0
T3	73107	0	0	0
T8	0	56	0	0
T10	0	7	0	0
T14	1982	4	0	0
T15	2694	0	0	0
T16	782	0	0	0
T17	988	0	0	0
T18	18490	0	0	0
T19	2212	1	0	0
T20	2621	0	0	0
T35	0	6	0	0
T37	0	1	0	0
T38	1714	0	0	0
T41	0	13	0	0
T104	723	0	0	0
T185	0	1	0	0
T186	0	15	0	0
T187	0	13	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T35,T36
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	204087749	4411	0	0
CgEnOn_A	204087749	2373	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	204087749	4411	0	0
T1	226662	1	0	0
T2	54963	1	0	0
T4	65249	1	0	0
T5	4813	1	0	0
T6	8103	1	0	0
T14	4016	5	0	0
T15	5107	1	0	0
T16	1670	1	0	0
T17	2053	1	0	0
T18	37073	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	204087749	2373	0	0
T3	146279	0	0	0
T8	0	55	0	0
T10	0	8	0	0
T14	4016	4	0	0
T15	5107	0	0	0
T16	1670	0	0	0
T17	2053	0	0	0
T18	37073	0	0	0
T19	4545	1	0	0
T20	5349	0	0	0
T35	0	6	0	0
T37	0	1	0	0
T38	3037	0	0	0
T41	0	14	0	0
T104	1491	0	0	0
T185	0	1	0	0
T186	0	16	0	0
T187	0	14	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T35,T36
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	104045403	4419	0	0
CgEnOn_A	104045403	2381	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104045403	4419	0	0
T1	113337	1	0	0
T2	27483	1	0	0
T4	32626	1	0	0
T5	2406	1	0	0
T6	4051	1	0	0
T14	2111	4	0	0
T15	2553	1	0	0
T16	835	1	0	0
T17	1026	1	0	0
T18	24298	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104045403	2381	0	0
T3	73143	0	0	0
T8	0	56	0	0
T10	0	7	0	0
T14	2111	3	0	0
T15	2553	0	0	0
T16	835	0	0	0
T17	1026	0	0	0
T18	24298	0	0	0
T19	2272	1	0	0
T20	2674	0	0	0
T35	0	5	0	0
T37	0	1	0	0
T38	1519	0	0	0
T41	0	12	0	0
T104	745	0	0	0
T185	0	1	0	0
T186	0	16	0	0
T187	0	12	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T8,T10
1	0	Covered	T19,T20,T34
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	216807734	2050	0	0
CgEnOn_A	216807734	2050	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216807734	2050	0	0
T3	152379	0	0	0
T8	0	51	0	0
T10	0	1	0	0
T14	4111	3	0	0
T15	5319	0	0	0
T16	1739	0	0	0
T17	2138	0	0	0
T18	44621	0	0	0
T19	4735	1	0	0
T20	5572	10	0	0
T34	0	1	0	0
T35	0	4	0	0
T37	0	1	0	0
T38	3164	0	0	0
T78	0	5	0	0
T79	0	7	0	0
T104	1554	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216807734	2050	0	0
T3	152379	0	0	0
T8	0	51	0	0
T10	0	1	0	0
T14	4111	3	0	0
T15	5319	0	0	0
T16	1739	0	0	0
T17	2138	0	0	0
T18	44621	0	0	0
T19	4735	1	0	0
T20	5572	10	0	0
T34	0	1	0	0
T35	0	4	0	0
T37	0	1	0	0
T38	3164	0	0	0
T78	0	5	0	0
T79	0	7	0	0
T104	1554	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T8,T10
1	0	Covered	T19,T20,T34
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	216807734	1996	0	0
CgEnOn_A	216807734	1996	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216807734	1996	0	0
T3	152379	0	0	0
T8	0	58	0	0
T10	0	1	0	0
T14	4111	3	0	0
T15	5319	0	0	0
T16	1739	0	0	0
T17	2138	0	0	0
T18	44621	0	0	0
T19	4735	1	0	0
T20	5572	7	0	0
T34	0	2	0	0
T35	0	4	0	0
T37	0	1	0	0
T38	3164	0	0	0
T78	0	3	0	0
T79	0	11	0	0
T104	1554	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216807734	1996	0	0
T3	152379	0	0	0
T8	0	58	0	0
T10	0	1	0	0
T14	4111	3	0	0
T15	5319	0	0	0
T16	1739	0	0	0
T17	2138	0	0	0
T18	44621	0	0	0
T19	4735	1	0	0
T20	5572	7	0	0
T34	0	2	0	0
T35	0	4	0	0
T37	0	1	0	0
T38	3164	0	0	0
T78	0	3	0	0
T79	0	11	0	0
T104	1554	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T8,T10
1	0	Covered	T19,T20,T34
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	216807734	2038	0	0
CgEnOn_A	216807734	2038	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216807734	2038	0	0
T3	152379	0	0	0
T8	0	43	0	0
T10	0	1	0	0
T14	4111	3	0	0
T15	5319	0	0	0
T16	1739	0	0	0
T17	2138	0	0	0
T18	44621	0	0	0
T19	4735	1	0	0
T20	5572	6	0	0
T34	0	3	0	0
T35	0	4	0	0
T37	0	1	0	0
T38	3164	0	0	0
T78	0	5	0	0
T79	0	9	0	0
T104	1554	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216807734	2038	0	0
T3	152379	0	0	0
T8	0	43	0	0
T10	0	1	0	0
T14	4111	3	0	0
T15	5319	0	0	0
T16	1739	0	0	0
T17	2138	0	0	0
T18	44621	0	0	0
T19	4735	1	0	0
T20	5572	6	0	0
T34	0	3	0	0
T35	0	4	0	0
T37	0	1	0	0
T38	3164	0	0	0
T78	0	5	0	0
T79	0	9	0	0
T104	1554	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T8,T10
1	0	Covered	T19,T20,T34
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	216807734	2051	0	0
CgEnOn_A	216807734	2051	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216807734	2051	0	0
T3	152379	0	0	0
T8	0	53	0	0
T10	0	1	0	0
T14	4111	3	0	0
T15	5319	0	0	0
T16	1739	0	0	0
T17	2138	0	0	0
T18	44621	0	0	0
T19	4735	1	0	0
T20	5572	6	0	0
T34	0	6	0	0
T35	0	4	0	0
T37	0	1	0	0
T38	3164	0	0	0
T78	0	3	0	0
T79	0	7	0	0
T104	1554	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216807734	2051	0	0
T3	152379	0	0	0
T8	0	53	0	0
T10	0	1	0	0
T14	4111	3	0	0
T15	5319	0	0	0
T16	1739	0	0	0
T17	2138	0	0	0
T18	44621	0	0	0
T19	4735	1	0	0
T20	5572	6	0	0
T34	0	6	0	0
T35	0	4	0	0
T37	0	1	0	0
T38	3164	0	0	0
T78	0	3	0	0
T79	0	7	0	0
T104	1554	0	0	0