Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	318076	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1496525

1

T1

74985

T5

25

T2

98

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	466602	1			T1	20936		T5	40		T2	32
values[0x0]	622710	1			T1	30528		T5	14		T2	81
values[0x1]	725289	1			T1	36437		T5	16		T2	89

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	188688	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1625913

1

T1

80894

T5

34

T2

121

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8619	1			T1	510		T6	2		T61	2
valid_sources[0x01]	6742	1			T1	297		T6	1		T3	23
valid_sources[0x02]	7093	1			T1	353		T16	1		T20	2
valid_sources[0x03]	7430	1			T1	264		T16	1		T6	1
valid_sources[0x04]	7461	1			T1	459		T83	1		T23	4
valid_sources[0x05]	6893	1			T1	309		T23	2		T98	1
valid_sources[0x06]	7063	1			T1	540		T3	12		T23	4
valid_sources[0x07]	7044	1			T1	210		T18	2		T61	1
valid_sources[0x08]	7396	1			T1	345		T23	4		T97	1
valid_sources[0x09]	7126	1			T1	409		T18	3		T20	1
valid_sources[0x0a]	6713	1			T1	451		T18	2		T3	3
valid_sources[0x0b]	7084	1			T1	347		T18	2		T6	1
valid_sources[0x0c]	7554	1			T1	354		T18	1		T6	2
valid_sources[0x0d]	6405	1			T1	358		T18	1		T83	1
valid_sources[0x0e]	6949	1			T1	319		T18	1		T3	106
valid_sources[0x0f]	5962	1			T1	471		T16	1		T6	1
valid_sources[0x10]	7571	1			T1	386		T18	1		T23	1
valid_sources[0x11]	7016	1			T1	264		T18	3		T61	3
valid_sources[0x12]	7256	1			T1	342		T88	2		T3	1
valid_sources[0x13]	6854	1			T1	366		T84	1		T23	2
valid_sources[0x14]	9224	1			T1	261		T18	1		T6	1
valid_sources[0x15]	7211	1			T1	397		T18	4		T20	1
valid_sources[0x16]	6658	1			T1	403		T18	1		T83	4
valid_sources[0x17]	6976	1			T1	314		T18	1		T3	12
valid_sources[0x18]	8522	1			T1	275		T16	2		T17	4
valid_sources[0x19]	7869	1			T1	289		T18	1		T20	1
valid_sources[0x1a]	6790	1			T1	444		T6	1		T23	3
valid_sources[0x1b]	5968	1			T1	327		T18	3		T23	4
valid_sources[0x1c]	6827	1			T1	337		T16	1		T18	2
valid_sources[0x1d]	6067	1			T1	242		T6	2		T84	1
valid_sources[0x1e]	6538	1			T1	307		T61	1		T3	9
valid_sources[0x1f]	6565	1			T1	285		T18	3		T3	5
valid_sources[0x20]	7100	1			T1	336		T18	1		T3	10
valid_sources[0x21]	7208	1			T1	317		T18	1		T84	1
valid_sources[0x22]	7103	1			T1	325		T3	21		T23	3
valid_sources[0x23]	7081	1			T1	266		T6	1		T23	1
valid_sources[0x24]	8004	1			T1	425		T16	1		T18	1
valid_sources[0x25]	7612	1			T1	323		T88	3		T55	3
valid_sources[0x26]	7418	1			T1	352		T18	8		T6	1
valid_sources[0x27]	7434	1			T1	459		T6	1		T23	2
valid_sources[0x28]	7597	1			T1	256		T16	1		T18	1
valid_sources[0x29]	7620	1			T1	410		T18	5		T3	9
valid_sources[0x2a]	9411	1			T1	339		T16	1		T6	1
valid_sources[0x2b]	6328	1			T1	287		T18	1		T3	10
valid_sources[0x2c]	6654	1			T1	354		T127	1		T11	199
valid_sources[0x2d]	6556	1			T1	348		T16	1		T83	13
valid_sources[0x2e]	7239	1			T1	290		T16	2		T18	2
valid_sources[0x2f]	6335	1			T1	286		T18	5		T6	3
valid_sources[0x30]	6782	1			T1	408		T9	1		T10	4
valid_sources[0x31]	7162	1			T1	431		T18	2		T6	1
valid_sources[0x32]	7401	1			T1	351		T20	1		T3	11
valid_sources[0x33]	7514	1			T1	279		T18	1		T61	1
valid_sources[0x34]	8095	1			T1	285		T18	2		T84	1
valid_sources[0x35]	7149	1			T1	459		T8	1		T9	4
valid_sources[0x36]	7032	1			T1	383		T18	2		T23	8
valid_sources[0x37]	7441	1			T1	354		T83	8		T3	10
valid_sources[0x38]	6660	1			T1	382		T16	1		T18	1
valid_sources[0x39]	6995	1			T1	467		T18	3		T3	13
valid_sources[0x3a]	6715	1			T1	327		T3	12		T23	2
valid_sources[0x3b]	7262	1			T1	320		T16	1		T18	1
valid_sources[0x3c]	6765	1			T1	363		T16	1		T6	1
valid_sources[0x3d]	7033	1			T1	320		T6	1		T3	27
valid_sources[0x3e]	7541	1			T1	353		T25	9		T11	192
valid_sources[0x3f]	7236	1			T1	294		T18	2		T6	2
valid_sources[0x40]	8612	1			T1	302		T18	1		T3	9
valid_sources[0x41]	6439	1			T1	407		T6	1		T23	1
valid_sources[0x42]	6516	1			T1	231		T20	1		T6	1
valid_sources[0x43]	6437	1			T1	395		T6	1		T61	1
valid_sources[0x44]	7136	1			T1	308		T18	1		T20	2
valid_sources[0x45]	7003	1			T1	260		T18	2		T20	3
valid_sources[0x46]	6584	1			T1	326		T18	1		T6	2
valid_sources[0x47]	6956	1			T1	463		T18	1		T20	1
valid_sources[0x48]	6720	1			T1	384		T61	3		T3	24
valid_sources[0x49]	6693	1			T1	285		T18	1		T6	1
valid_sources[0x4a]	6389	1			T1	221		T18	3		T88	1
valid_sources[0x4b]	7479	1			T1	282		T6	1		T127	1
valid_sources[0x4c]	6071	1			T1	453		T16	1		T18	1
valid_sources[0x4d]	6971	1			T1	363		T6	1		T3	34
valid_sources[0x4e]	7310	1			T1	304		T18	1		T6	1
valid_sources[0x4f]	6872	1			T1	330		T18	1		T3	3
valid_sources[0x50]	7387	1			T1	299		T18	4		T23	2
valid_sources[0x51]	6945	1			T1	350		T18	2		T6	1
valid_sources[0x52]	6697	1			T1	322		T19	56		T6	1
valid_sources[0x53]	6950	1			T1	348		T18	2		T3	9
valid_sources[0x54]	6503	1			T1	380		T18	1		T20	2
valid_sources[0x55]	6489	1			T1	356		T18	3		T6	2
valid_sources[0x56]	6665	1			T1	461		T18	5		T23	4
valid_sources[0x57]	7066	1			T1	260		T18	2		T20	2
valid_sources[0x58]	7137	1			T1	253		T6	1		T3	15
valid_sources[0x59]	7765	1			T1	422		T16	2		T18	1
valid_sources[0x5a]	6688	1			T1	313		T18	3		T84	1
valid_sources[0x5b]	6664	1			T1	324		T18	1		T6	1
valid_sources[0x5c]	6924	1			T1	285		T18	1		T20	1
valid_sources[0x5d]	6182	1			T1	351		T18	3		T6	1
valid_sources[0x5e]	7931	1			T1	332		T6	1		T3	21
valid_sources[0x5f]	7473	1			T1	274		T6	2		T3	34
valid_sources[0x60]	7248	1			T1	461		T3	4		T23	1
valid_sources[0x61]	6528	1			T1	336		T18	3		T23	1
valid_sources[0x62]	8579	1			T1	498		T6	2		T84	1
valid_sources[0x63]	7582	1			T1	305		T18	4		T6	1
valid_sources[0x64]	7080	1			T1	307		T6	1		T23	1
valid_sources[0x65]	7187	1			T1	443		T6	2		T3	7
valid_sources[0x66]	6011	1			T1	305		T18	3		T6	2
valid_sources[0x67]	6853	1			T1	332		T18	4		T3	10
valid_sources[0x68]	6920	1			T1	230		T6	2		T3	24
valid_sources[0x69]	6643	1			T1	229		T18	5		T3	14
valid_sources[0x6a]	6699	1			T1	250		T16	1		T6	1
valid_sources[0x6b]	7698	1			T1	296		T18	4		T6	2
valid_sources[0x6c]	6663	1			T1	389		T18	6		T3	47
valid_sources[0x6d]	6812	1			T1	386		T16	1		T18	2
valid_sources[0x6e]	6705	1			T1	360		T18	1		T6	1
valid_sources[0x6f]	7440	1			T1	263		T23	1		T9	1
valid_sources[0x70]	6381	1			T1	335		T6	1		T83	1
valid_sources[0x71]	6053	1			T1	211		T18	4		T61	1
valid_sources[0x72]	7964	1			T1	579		T6	2		T88	1
valid_sources[0x73]	7015	1			T1	236		T20	1		T3	14
valid_sources[0x74]	6881	1			T1	359		T6	1		T23	3
valid_sources[0x75]	7211	1			T1	371		T18	1		T83	7
valid_sources[0x76]	7346	1			T1	321		T3	3		T9	1
valid_sources[0x77]	9385	1			T1	332		T16	1		T18	1
valid_sources[0x78]	6888	1			T1	321		T3	1		T23	1
valid_sources[0x79]	7281	1			T1	455		T6	2		T83	1
valid_sources[0x7a]	6660	1			T1	289		T61	1		T88	1
valid_sources[0x7b]	6987	1			T1	273		T18	2		T83	3
valid_sources[0x7c]	7519	1			T1	289		T18	4		T3	50
valid_sources[0x7d]	6407	1			T1	313		T6	1		T97	4
valid_sources[0x7e]	9450	1			T1	200		T18	2		T61	1
valid_sources[0x7f]	7455	1			T1	400		T18	1		T6	1
valid_sources[0x80]	6860	1			T1	228		T20	1		T6	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

386253

1

T1

18750

T5

17

T2

13

values[0x0]

all_enables

biggest_size

569327

1

T1

28430

T5

5

T2

50

values[0x1]

all_enables

biggest_size

540945

1

T1

27805

T5

3

T2

35