Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T6
0	1	Covered	T1,T88,T3
1	0	Covered	T1,T5,T2

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Covered	T29,T30,T31
1	1	Covered	T1,T5,T2

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	612200687	7883	0	0
GateOpen_A	612200687	14485	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	612200687	7883	0	0
T1	910347	579	0	0
T2	198496	0	0	0
T3	0	120	0	0
T4	236827	0	0	0
T5	15795	0	0	0
T15	9099	0	0	0
T16	4666	0	0	0
T17	5104	0	0	0
T18	243162	0	0	0
T19	16368	0	0	0
T20	5164	0	0	0
T29	0	4	0	0
T30	0	22	0	0
T31	0	9	0	0
T32	0	4	0	0
T88	0	34	0	0
T102	0	4	0	0
T104	0	4	0	0
T128	0	34	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	612200687	14485	0	0
T1	910347	607	0	0
T2	198496	0	0	0
T4	236827	76	0	0
T5	15795	0	0	0
T6	0	20	0	0
T15	9099	0	0	0
T16	4666	4	0	0
T17	5104	4	0	0
T18	243162	0	0	0
T19	16368	0	0	0
T20	5164	4	0	0
T26	0	4	0	0
T29	0	8	0	0
T84	0	4	0	0
T88	0	38	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T6
0	1	Covered	T1,T88,T3
1	0	Covered	T1,T5,T2

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Covered	T29,T30,T31
1	1	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	67487325	1883	0	0
GateOpen_A	67487325	3533	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67487325	1883	0	0
T1	505308	143	0	0
T2	22033	0	0	0
T3	0	31	0	0
T4	16873	0	0	0
T5	1737	0	0	0
T15	1032	0	0	0
T16	506	0	0	0
T17	554	0	0	0
T18	26374	0	0	0
T19	1803	0	0	0
T20	576	0	0	0
T29	0	1	0	0
T30	0	6	0	0
T31	0	2	0	0
T32	0	1	0	0
T88	0	8	0	0
T102	0	1	0	0
T104	0	1	0	0
T128	0	9	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67487325	3533	0	0
T1	505308	150	0	0
T2	22033	0	0	0
T4	16873	19	0	0
T5	1737	0	0	0
T6	0	5	0	0
T15	1032	0	0	0
T16	506	1	0	0
T17	554	1	0	0
T18	26374	0	0	0
T19	1803	0	0	0
T20	576	1	0	0
T26	0	1	0	0
T29	0	2	0	0
T84	0	1	0	0
T88	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T6
0	1	Covered	T1,T88,T3
1	0	Covered	T1,T5,T2

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Covered	T29,T30,T31
1	1	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	134975088	2001	0	0
GateOpen_A	134975088	3651	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134975088	2001	0	0
T1	101062	145	0	0
T2	44065	0	0	0
T3	0	30	0	0
T4	33742	0	0	0
T5	3474	0	0	0
T15	2064	0	0	0
T16	1014	0	0	0
T17	1108	0	0	0
T18	52748	0	0	0
T19	3606	0	0	0
T20	1153	0	0	0
T29	0	1	0	0
T30	0	6	0	0
T31	0	2	0	0
T32	0	1	0	0
T88	0	8	0	0
T102	0	1	0	0
T104	0	1	0	0
T128	0	7	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134975088	3651	0	0
T1	101062	152	0	0
T2	44065	0	0	0
T4	33742	19	0	0
T5	3474	0	0	0
T6	0	5	0	0
T15	2064	0	0	0
T16	1014	1	0	0
T17	1108	1	0	0
T18	52748	0	0	0
T19	3606	0	0	0
T20	1153	1	0	0
T26	0	1	0	0
T29	0	2	0	0
T84	0	1	0	0
T88	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T6
0	1	Covered	T1,T88,T3
1	0	Covered	T1,T5,T2

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Covered	T29,T30,T31
1	1	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	271334223	1997	0	0
GateOpen_A	271334223	3648	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	271334223	1997	0	0
T1	201746	144	0	0
T2	88264	0	0	0
T3	0	29	0	0
T4	124139	0	0	0
T5	7056	0	0	0
T15	4002	0	0	0
T16	2097	0	0	0
T17	2295	0	0	0
T18	105519	0	0	0
T19	7306	0	0	0
T20	2290	0	0	0
T29	0	1	0	0
T30	0	6	0	0
T31	0	2	0	0
T32	0	1	0	0
T88	0	9	0	0
T102	0	1	0	0
T104	0	1	0	0
T128	0	8	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	271334223	3648	0	0
T1	201746	151	0	0
T2	88264	0	0	0
T4	124139	19	0	0
T5	7056	0	0	0
T6	0	5	0	0
T15	4002	0	0	0
T16	2097	1	0	0
T17	2295	1	0	0
T18	105519	0	0	0
T19	7306	0	0	0
T20	2290	1	0	0
T26	0	1	0	0
T29	0	2	0	0
T84	0	1	0	0
T88	0	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T6
0	1	Covered	T1,T88,T3
1	0	Covered	T1,T5,T2

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Covered	T29,T30,T31
1	1	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	138404051	2002	0	0
GateOpen_A	138404051	3653	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138404051	2002	0	0
T1	102231	147	0	0
T2	44134	0	0	0
T3	0	30	0	0
T4	62073	0	0	0
T5	3528	0	0	0
T15	2001	0	0	0
T16	1049	0	0	0
T17	1147	0	0	0
T18	58521	0	0	0
T19	3653	0	0	0
T20	1145	0	0	0
T29	0	1	0	0
T30	0	4	0	0
T31	0	3	0	0
T32	0	1	0	0
T88	0	9	0	0
T102	0	1	0	0
T104	0	1	0	0
T128	0	10	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138404051	3653	0	0
T1	102231	154	0	0
T2	44134	0	0	0
T4	62073	19	0	0
T5	3528	0	0	0
T6	0	5	0	0
T15	2001	0	0	0
T16	1049	1	0	0
T17	1147	1	0	0
T18	58521	0	0	0
T19	3653	0	0	0
T20	1145	1	0	0
T26	0	1	0	0
T29	0	2	0	0
T84	0	1	0	0
T88	0	10	0	0