Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	365525085	34802	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365525085	34802	0	0
T1	1176995	867	0	0
T2	353985	242	0	0
T3	0	554	0	0
T4	646575	0	0	0
T5	8815	0	0	0
T8	0	93	0	0
T9	0	93	0	0
T10	0	615	0	0
T11	0	368	0	0
T12	0	328	0	0
T13	0	692	0	0
T14	0	1224	0	0
T15	5835	0	0	0
T16	10480	0	0	0
T17	5975	0	0	0
T18	729595	0	0	0
T19	9125	0	0	0
T20	11685	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	73105017	5200	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73105017	5200	0	0
T1	235399	161	0	0
T2	70797	31	0	0
T3	0	87	0	0
T4	129315	0	0	0
T5	1763	0	0	0
T8	0	14	0	0
T9	0	15	0	0
T10	0	79	0	0
T11	0	59	0	0
T12	0	44	0	0
T13	0	90	0	0
T14	0	238	0	0
T15	1167	0	0	0
T16	2096	0	0	0
T17	1195	0	0	0
T18	145919	0	0	0
T19	1825	0	0	0
T20	2337	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	73105017	5125	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73105017	5125	0	0
T1	235399	161	0	0
T2	70797	31	0	0
T3	0	86	0	0
T4	129315	0	0	0
T5	1763	0	0	0
T8	0	11	0	0
T9	0	15	0	0
T10	0	88	0	0
T11	0	57	0	0
T12	0	48	0	0
T13	0	88	0	0
T14	0	238	0	0
T15	1167	0	0	0
T16	2096	0	0	0
T17	1195	0	0	0
T18	145919	0	0	0
T19	1825	0	0	0
T20	2337	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	73105017	6990	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73105017	6990	0	0
T1	235399	166	0	0
T2	70797	49	0	0
T3	0	113	0	0
T4	129315	0	0	0
T5	1763	0	0	0
T8	0	18	0	0
T9	0	19	0	0
T10	0	121	0	0
T11	0	76	0	0
T12	0	64	0	0
T13	0	140	0	0
T14	0	238	0	0
T15	1167	0	0	0
T16	2096	0	0	0
T17	1195	0	0	0
T18	145919	0	0	0
T19	1825	0	0	0
T20	2337	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	73105017	6976	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73105017	6976	0	0
T1	235399	169	0	0
T2	70797	51	0	0
T3	0	114	0	0
T4	129315	0	0	0
T5	1763	0	0	0
T8	0	20	0	0
T9	0	19	0	0
T10	0	119	0	0
T11	0	73	0	0
T12	0	65	0	0
T13	0	140	0	0
T14	0	238	0	0
T15	1167	0	0	0
T16	2096	0	0	0
T17	1195	0	0	0
T18	145919	0	0	0
T19	1825	0	0	0
T20	2337	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	73105017	10511	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73105017	10511	0	0
T1	235399	210	0	0
T2	70797	80	0	0
T3	0	154	0	0
T4	129315	0	0	0
T5	1763	0	0	0
T8	0	30	0	0
T9	0	25	0	0
T10	0	208	0	0
T11	0	103	0	0
T12	0	107	0	0
T13	0	234	0	0
T14	0	272	0	0
T15	1167	0	0	0
T16	2096	0	0	0
T17	1195	0	0	0
T18	145919	0	0	0
T19	1825	0	0	0
T20	2337	0	0	0