Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T2
0	1	Unreachable
1	0	Covered	T1,T4,T6

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	73105017	70763769	0	0
AllClkBypReqTrue_A	73105017	82062	0	0
IoClkBypReqFalse_A	73105017	70707851	0	2322
IoClkBypReqTrue_A	73105017	133556	0	0
LcClkBypAckFalse_A	73105017	70768796	0	0
LcClkBypAckTrue_A	73105017	77035	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73105017	70763769	0	0
T1	235399	235002	0	0
T2	70797	70622	0	0
T4	129315	5217	0	0
T5	1763	1701	0	0
T15	1167	1073	0	0
T16	2096	1810	0	0
T17	1195	1095	0	0
T18	145919	145806	0	0
T19	1825	1795	0	0
T20	2337	1982	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73105017	82062	0	0
T1	235399	3368	0	0
T2	70797	0	0	0
T4	129315	0	0	0
T5	1763	0	0	0
T11	0	1134	0	0
T15	1167	34	0	0
T16	2096	109	0	0
T17	1195	0	0	0
T18	145919	0	0	0
T19	1825	0	0	0
T20	2337	105	0	0
T87	0	161	0	0
T97	0	245	0	0
T98	0	4	0	0
T99	0	10	0	0
T100	0	15	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73105017	70707851	0	2322
T1	235399	234783	0	3
T2	70797	70620	0	3
T4	129315	5179	0	3
T5	1763	1699	0	3
T15	1167	993	0	3
T16	2096	1917	0	3
T17	1195	1093	0	3
T18	145919	145804	0	3
T19	1825	1793	0	3
T20	2337	1862	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73105017	133556	0	0
T1	235399	5536	0	0
T2	70797	0	0	0
T4	129315	0	0	0
T5	1763	0	0	0
T11	0	1362	0	0
T12	0	815	0	0
T15	1167	112	0	0
T16	2096	0	0	0
T17	1195	0	0	0
T18	145919	0	0	0
T19	1825	0	0	0
T20	2337	223	0	0
T87	0	174	0	0
T97	0	455	0	0
T98	0	333	0	0
T100	0	19	0	0
T101	0	148	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73105017	70768796	0	0
T1	235399	234981	0	0
T2	70797	70622	0	0
T4	129315	5217	0	0
T5	1763	1701	0	0
T15	1167	1045	0	0
T16	2096	1919	0	0
T17	1195	1095	0	0
T18	145919	145806	0	0
T19	1825	1795	0	0
T20	2337	1975	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73105017	77035	0	0
T1	235399	3572	0	0
T2	70797	0	0	0
T4	129315	0	0	0
T5	1763	0	0	0
T11	0	804	0	0
T12	0	481	0	0
T15	1167	62	0	0
T16	2096	0	0	0
T17	1195	0	0	0
T18	145919	0	0	0
T19	1825	0	0	0
T20	2337	112	0	0
T87	0	24	0	0
T97	0	338	0	0
T98	0	134	0	0
T100	0	14	0	0
T101	0	64	0	0