Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1153084628	9087	0	0
TransStop_A	1153084628	4773	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1153084628	9087	0	0
T1	851916	371	0	0
T2	367776	0	0	0
T3	0	61	0	0
T4	517264	0	0	0
T5	29400	15	0	0
T11	0	5	0	0
T15	16676	0	0	0
T16	8736	0	0	0
T17	9564	0	0	0
T18	583680	0	0	0
T19	30440	14	0	0
T20	9540	0	0	0
T32	0	4	0	0
T55	0	1	0	0
T61	0	14	0	0
T83	0	32	0	0
T84	0	4	0	0
T102	0	4	0	0
T103	0	2	0	0
T104	0	2	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1153084628	4773	0	0
T1	851916	168	0	0
T2	367776	0	0	0
T3	0	41	0	0
T4	517264	0	0	0
T5	29400	9	0	0
T11	0	2	0	0
T15	16676	0	0	0
T16	8736	0	0	0
T17	9564	0	0	0
T18	583680	0	0	0
T19	30440	10	0	0
T20	9540	0	0	0
T32	0	4	0	0
T61	0	9	0	0
T83	0	27	0	0
T84	0	4	0	0
T102	0	4	0	0
T103	0	3	0	0
T104	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	288271157	2217	0	0
TransStop_A	288271157	1184	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	288271157	2217	0	0
T1	212979	87	0	0
T2	91944	0	0	0
T3	0	15	0	0
T4	129316	0	0	0
T5	7350	4	0	0
T15	4169	0	0	0
T16	2184	0	0	0
T17	2391	0	0	0
T18	145920	0	0	0
T19	7610	3	0	0
T20	2385	0	0	0
T32	0	1	0	0
T55	0	1	0	0
T61	0	3	0	0
T83	0	8	0	0
T84	0	1	0	0
T102	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	288271157	1184	0	0
T1	212979	39	0	0
T2	91944	0	0	0
T3	0	9	0	0
T4	129316	0	0	0
T5	7350	2	0	0
T15	4169	0	0	0
T16	2184	0	0	0
T17	2391	0	0	0
T18	145920	0	0	0
T19	7610	3	0	0
T20	2385	0	0	0
T32	0	1	0	0
T61	0	2	0	0
T83	0	8	0	0
T84	0	1	0	0
T102	0	1	0	0
T103	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	288271157	2237	0	0
TransStop_A	288271157	1170	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	288271157	2237	0	0
T1	212979	93	0	0
T2	91944	0	0	0
T3	0	17	0	0
T4	129316	0	0	0
T5	7350	2	0	0
T11	0	5	0	0
T15	4169	0	0	0
T16	2184	0	0	0
T17	2391	0	0	0
T18	145920	0	0	0
T19	7610	4	0	0
T20	2385	0	0	0
T32	0	1	0	0
T61	0	4	0	0
T83	0	8	0	0
T102	0	1	0	0
T104	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	288271157	1170	0	0
T1	212979	43	0	0
T2	91944	0	0	0
T3	0	12	0	0
T4	129316	0	0	0
T5	7350	2	0	0
T11	0	2	0	0
T15	4169	0	0	0
T16	2184	0	0	0
T17	2391	0	0	0
T18	145920	0	0	0
T19	7610	3	0	0
T20	2385	0	0	0
T32	0	1	0	0
T61	0	3	0	0
T83	0	6	0	0
T102	0	1	0	0
T104	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	288271157	2366	0	0
TransStop_A	288271157	1255	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	288271157	2366	0	0
T1	212979	100	0	0
T2	91944	0	0	0
T3	0	17	0	0
T4	129316	0	0	0
T5	7350	4	0	0
T15	4169	0	0	0
T16	2184	0	0	0
T17	2391	0	0	0
T18	145920	0	0	0
T19	7610	5	0	0
T20	2385	0	0	0
T32	0	1	0	0
T61	0	4	0	0
T83	0	8	0	0
T84	0	1	0	0
T102	0	1	0	0
T103	0	2	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	288271157	1255	0	0
T1	212979	52	0	0
T2	91944	0	0	0
T3	0	12	0	0
T4	129316	0	0	0
T5	7350	3	0	0
T15	4169	0	0	0
T16	2184	0	0	0
T17	2391	0	0	0
T18	145920	0	0	0
T19	7610	2	0	0
T20	2385	0	0	0
T32	0	1	0	0
T61	0	3	0	0
T83	0	6	0	0
T84	0	1	0	0
T102	0	1	0	0
T103	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	288271157	2267	0	0
TransStop_A	288271157	1164	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	288271157	2267	0	0
T1	212979	91	0	0
T2	91944	0	0	0
T3	0	12	0	0
T4	129316	0	0	0
T5	7350	5	0	0
T15	4169	0	0	0
T16	2184	0	0	0
T17	2391	0	0	0
T18	145920	0	0	0
T19	7610	2	0	0
T20	2385	0	0	0
T32	0	1	0	0
T61	0	3	0	0
T83	0	8	0	0
T84	0	2	0	0
T102	0	1	0	0
T104	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	288271157	1164	0	0
T1	212979	34	0	0
T2	91944	0	0	0
T3	0	8	0	0
T4	129316	0	0	0
T5	7350	2	0	0
T15	4169	0	0	0
T16	2184	0	0	0
T17	2391	0	0	0
T18	145920	0	0	0
T19	7610	2	0	0
T20	2385	0	0	0
T32	0	1	0	0
T61	0	1	0	0
T83	0	7	0	0
T84	0	2	0	0
T102	0	1	0	0
T104	0	1	0	0