Module Definition
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Module : prim_generic_clock_mux2
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_div2.u_step_down_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T5,T2
01CoveredT1,T5,T2
10CoveredT1,T15,T16 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T5,T2
10CoveredT1,T15,T16
11CoveredT1,T15,T16 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT1,T15,T16
10CoveredT1,T5,T2
11CoveredT1,T5,T2
Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 337199995 337197673 0 0
selKnown1 814001436 813999114 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 337199995 337197673 0 0
T1 707230 707228 0 0
T2 110160 110157 0 0
T4 84356 84353 0 0
T5 8685 8682 0 0
T15 5041 5038 0 0
T16 2507 2504 0 0
T17 2770 2767 0 0
T18 131868 131865 0 0
T19 9015 9012 0 0
T20 2811 2808 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 814001436 813999114 0 0
T1 605238 605238 0 0
T2 264789 264786 0 0
T4 372417 372414 0 0
T5 21165 21162 0 0
T15 12003 12000 0 0
T16 6288 6285 0 0
T17 6882 6879 0 0
T18 316557 316554 0 0
T19 21915 21912 0 0
T20 6867 6864 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T5,T2
01CoveredT1,T5,T2
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T5,T2
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT1,T5,T2
11CoveredT1,T5,T2
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 134974715 134973941 0 0
selKnown1 271333812 271333038 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 134974715 134973941 0 0
T1 101062 101061 0 0
T2 44064 44063 0 0
T4 33742 33741 0 0
T5 3474 3473 0 0
T15 2063 2062 0 0
T16 1014 1013 0 0
T17 1108 1107 0 0
T18 52747 52746 0 0
T19 3606 3605 0 0
T20 1152 1151 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 271333812 271333038 0 0
T1 201746 201746 0 0
T2 88263 88262 0 0
T4 124139 124138 0 0
T5 7055 7054 0 0
T15 4001 4000 0 0
T16 2096 2095 0 0
T17 2294 2293 0 0
T18 105519 105518 0 0
T19 7305 7304 0 0
T20 2289 2288 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T5,T2
01CoveredT1,T5,T2
10CoveredT1,T15,T16 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T5,T2
10CoveredT1,T15,T16
11CoveredT1,T15,T16 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT1,T15,T16
10CoveredT1,T5,T2
11CoveredT1,T5,T2
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 134738345 134737571 0 0
selKnown1 271333812 271333038 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 134738345 134737571 0 0
T1 100860 100860 0 0
T2 44064 44063 0 0
T4 33742 33741 0 0
T5 3474 3473 0 0
T15 1947 1946 0 0
T16 988 987 0 0
T17 1108 1107 0 0
T18 52747 52746 0 0
T19 3606 3605 0 0
T20 1084 1083 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 271333812 271333038 0 0
T1 201746 201746 0 0
T2 88263 88262 0 0
T4 124139 124138 0 0
T5 7055 7054 0 0
T15 4001 4000 0 0
T16 2096 2095 0 0
T17 2294 2293 0 0
T18 105519 105518 0 0
T19 7305 7304 0 0
T20 2289 2288 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T5,T2
01CoveredT1,T5,T2
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T5,T2
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT1,T5,T2
11CoveredT1,T5,T2
Assert Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 67486935 67486161 0 0
selKnown1 271333812 271333038 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 67486935 67486161 0 0
T1 505308 505307 0 0
T2 22032 22031 0 0
T4 16872 16871 0 0
T5 1737 1736 0 0
T15 1031 1030 0 0
T16 505 504 0 0
T17 554 553 0 0
T18 26374 26373 0 0
T19 1803 1802 0 0
T20 575 574 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 271333812 271333038 0 0
T1 201746 201746 0 0
T2 88263 88262 0 0
T4 124139 124138 0 0
T5 7055 7054 0 0
T15 4001 4000 0 0
T16 2096 2095 0 0
T17 2294 2293 0 0
T18 105519 105518 0 0
T19 7305 7304 0 0
T20 2289 2288 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%