Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	73105017	6633363	0	62

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73105017	6633363	0	62
T1	235399	39360	0	0
T2	70797	28816	0	1
T3	0	37462	0	0
T4	129315	0	0	0
T5	1763	0	0	0
T8	0	12507	0	1
T9	0	6936	0	1
T10	0	73068	0	1
T11	0	29293	0	0
T12	0	36813	0	0
T13	0	84485	0	0
T14	0	51558	0	0
T15	1167	0	0	0
T16	2096	0	0	0
T17	1195	0	0	0
T18	145919	0	0	0
T19	1825	0	0	0
T20	2337	0	0	0
T105	0	0	0	1
T106	0	0	0	1
T107	0	0	0	1
T108	0	0	0	1
T109	0	0	0	1
T110	0	0	0	1