Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	74129433	2123554	0	0
clk_enables_rd_A	74129433	13073	0	0
clk_hints_rd_A	74129433	12040	0	0
extclk_ctrl_rd_A	74129433	14985	0	0
extclk_ctrl_regwen_rd_A	74129433	10585	0	0
jitter_enable_rd_A	74129433	17069	0	0
jitter_regwen_rd_A	74129433	11509	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74129433	2123554	0	0
T1	235399	108933	0	0
T2	70797	0	0	0
T4	129315	0	0	0
T5	1763	0	0	0
T11	0	67873	0	0
T14	0	102647	0	0
T15	1167	0	0	0
T16	2096	0	0	0
T17	1195	0	0	0
T18	145919	0	0	0
T19	1825	0	0	0
T20	2337	0	0	0
T21	0	41396	0	0
T28	0	137324	0	0
T56	0	102641	0	0
T57	0	108304	0	0
T58	0	71762	0	0
T59	0	101711	0	0
T60	0	211128	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74129433	13073	0	0
T8	99330	0	0	0
T14	0	4275	0	0
T27	1906	0	0	0
T31	1075	0	0	0
T32	2082	1	0	0
T41	0	7	0	0
T58	0	2470	0	0
T97	2362	0	0	0
T101	1268	0	0	0
T102	1589	0	0	0
T103	1126	0	0	0
T104	0	7	0	0
T122	0	4	0	0
T123	0	7	0	0
T124	0	6	0	0
T125	0	12	0	0
T126	0	5	0	0
T127	1749	0	0	0
T128	1415	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74129433	12040	0	0
T8	99330	0	0	0
T14	0	3761	0	0
T27	1906	0	0	0
T31	1075	0	0	0
T32	2082	10	0	0
T58	0	2124	0	0
T97	2362	0	0	0
T101	1268	0	0	0
T102	1589	0	0	0
T103	1126	0	0	0
T123	0	10	0	0
T125	0	4	0	0
T126	0	2	0	0
T127	1749	0	0	0
T128	1415	0	0	0
T129	0	2	0	0
T130	0	3	0	0
T131	0	1	0	0
T132	0	5	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74129433	14985	0	0
T9	44645	0	0	0
T10	235477	0	0	0
T14	0	4629	0	0
T24	75768	102	0	0
T25	15331	0	0	0
T36	0	49	0	0
T43	0	128	0	0
T100	1136	0	0	0
T104	1932	0	0	0
T111	0	40	0	0
T123	0	16	0	0
T133	0	1	0	0
T134	0	84	0	0
T135	0	31	0	0
T136	0	34	0	0
T137	1162	0	0	0
T138	1566	0	0	0
T139	1539	0	0	0
T140	1579	0	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74129433	10585	0	0
T9	44645	0	0	0
T10	235477	0	0	0
T14	0	3491	0	0
T24	75768	31	0	0
T25	15331	0	0	0
T43	0	50	0	0
T58	0	2224	0	0
T100	1136	0	0	0
T104	1932	0	0	0
T137	1162	0	0	0
T138	1566	0	0	0
T139	1539	0	0	0
T140	1579	0	0	0
T141	0	22	0	0
T142	0	26	0	0
T143	0	53	0	0
T144	0	23	0	0
T145	0	50	0	0
T146	0	67	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74129433	17069	0	0
T8	99330	0	0	0
T14	0	5902	0	0
T27	1906	0	0	0
T31	1075	0	0	0
T32	2082	91	0	0
T41	0	93	0	0
T97	2362	0	0	0
T101	1268	0	0	0
T102	1589	0	0	0
T103	1126	0	0	0
T104	0	65	0	0
T122	0	93	0	0
T123	0	247	0	0
T124	0	146	0	0
T127	1749	0	0	0
T128	1415	0	0	0
T129	0	102	0	0
T147	0	72	0	0
T148	0	44	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74129433	11509	0	0
T7	31851	0	0	0
T14	349641	3926	0	0
T21	119003	0	0	0
T48	0	197	0	0
T58	0	2670	0	0
T64	0	9	0	0
T67	0	36	0	0
T68	0	119	0	0
T81	0	31	0	0
T147	2419	0	0	0
T149	0	1877	0	0
T150	0	521	0	0
T151	0	4	0	0
T152	1599	0	0	0
T153	4335	0	0	0
T154	1096	0	0	0
T155	960	0	0	0
T156	1718	0	0	0
T157	885	0	0	0