Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	219315051	368	0	0
StatusRise_A	219315051	368	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219315051	368	0	0
T3	830862	0	0	0
T23	160341	0	0	0
T27	5718	0	0	0
T29	2778	5	0	0
T30	3768	16	0	0
T31	0	7	0	0
T32	6246	0	0	0
T39	0	2	0	0
T40	0	2	0	0
T55	2733	0	0	0
T88	4845	0	0	0
T102	4767	0	0	0
T127	5247	0	0	0
T137	0	4	0	0
T140	0	10	0	0
T157	0	4	0	0
T158	0	6	0	0
T159	0	7	0	0
T160	0	13	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	219315051	368	0	0
T3	830862	0	0	0
T23	160341	0	0	0
T27	5718	0	0	0
T29	2778	5	0	0
T30	3768	16	0	0
T31	0	7	0	0
T32	6246	0	0	0
T39	0	2	0	0
T40	0	2	0	0
T55	2733	0	0	0
T88	4845	0	0	0
T102	4767	0	0	0
T127	5247	0	0	0
T137	0	4	0	0
T140	0	10	0	0
T157	0	4	0	0
T158	0	6	0	0
T159	0	7	0	0
T160	0	13	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	73105017	120	0	0
StatusRise_A	73105017	120	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73105017	120	0	0
T3	276954	0	0	0
T23	53447	0	0	0
T27	1906	0	0	0
T29	926	3	0	0
T30	1256	6	0	0
T31	0	2	0	0
T32	2082	0	0	0
T40	0	1	0	0
T55	911	0	0	0
T88	1615	0	0	0
T102	1589	0	0	0
T127	1749	0	0	0
T137	0	1	0	0
T140	0	4	0	0
T157	0	1	0	0
T158	0	3	0	0
T159	0	2	0	0
T160	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73105017	120	0	0
T3	276954	0	0	0
T23	53447	0	0	0
T27	1906	0	0	0
T29	926	3	0	0
T30	1256	6	0	0
T31	0	2	0	0
T32	2082	0	0	0
T40	0	1	0	0
T55	911	0	0	0
T88	1615	0	0	0
T102	1589	0	0	0
T127	1749	0	0	0
T137	0	1	0	0
T140	0	4	0	0
T157	0	1	0	0
T158	0	3	0	0
T159	0	2	0	0
T160	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	73105017	121	0	0
StatusRise_A	73105017	121	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73105017	121	0	0
T3	276954	0	0	0
T23	53447	0	0	0
T27	1906	0	0	0
T29	926	1	0	0
T30	1256	6	0	0
T31	0	2	0	0
T32	2082	0	0	0
T39	0	2	0	0
T55	911	0	0	0
T88	1615	0	0	0
T102	1589	0	0	0
T127	1749	0	0	0
T137	0	2	0	0
T140	0	3	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	0	3	0	0
T160	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73105017	121	0	0
T3	276954	0	0	0
T23	53447	0	0	0
T27	1906	0	0	0
T29	926	1	0	0
T30	1256	6	0	0
T31	0	2	0	0
T32	2082	0	0	0
T39	0	2	0	0
T55	911	0	0	0
T88	1615	0	0	0
T102	1589	0	0	0
T127	1749	0	0	0
T137	0	2	0	0
T140	0	3	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	0	3	0	0
T160	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	73105017	127	0	0
StatusRise_A	73105017	127	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73105017	127	0	0
T3	276954	0	0	0
T23	53447	0	0	0
T27	1906	0	0	0
T29	926	1	0	0
T30	1256	4	0	0
T31	0	3	0	0
T32	2082	0	0	0
T40	0	1	0	0
T55	911	0	0	0
T88	1615	0	0	0
T102	1589	0	0	0
T127	1749	0	0	0
T137	0	1	0	0
T140	0	3	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	0	2	0	0
T160	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73105017	127	0	0
T3	276954	0	0	0
T23	53447	0	0	0
T27	1906	0	0	0
T29	926	1	0	0
T30	1256	4	0	0
T31	0	3	0	0
T32	2082	0	0	0
T40	0	1	0	0
T55	911	0	0	0
T88	1615	0	0	0
T102	1589	0	0	0
T127	1749	0	0	0
T137	0	1	0	0
T140	0	3	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	0	2	0	0
T160	0	5	0	0