Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	31320	0	0
CgEnOn_A	2147483647	22470	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	31320	0	0
T1	1762263	771	0	0
T2	566268	3	0	0
T3	2908829	0	0	0
T4	754085	57	0	0
T5	45189	7	0	0
T15	25768	3	0	0
T16	13399	3	0	0
T17	14663	3	0	0
T18	826837	3	0	0
T19	46802	6	0	0
T20	14697	3	0	0
T21	0	5	0	0
T23	217320	0	0	0
T27	9129	0	0	0
T29	17214	8	0	0
T30	10834	36	0	0
T31	0	10	0	0
T32	19250	0	0	0
T39	0	10	0	0
T55	24784	0	0	0
T61	0	3	0	0
T88	7719	0	0	0
T102	29478	0	0	0
T127	8390	0	0	0
T137	0	10	0	0
T140	0	15	0	0
T157	0	10	0	0
T158	0	10	0	0
T159	0	15	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	22470	0	0
T1	1762263	741	0	0
T2	566268	0	0	0
T3	2908829	152	0	0
T4	754085	0	0	0
T5	45189	4	0	0
T15	25768	0	0	0
T16	13399	0	0	0
T17	14663	0	0	0
T18	826837	0	0	0
T19	46802	3	0	0
T20	14697	0	0	0
T21	0	4	0	0
T23	217320	0	0	0
T27	9129	0	0	0
T29	17214	11	0	0
T30	10834	54	0	0
T31	0	16	0	0
T32	19250	3	0	0
T39	0	10	0	0
T55	24784	0	0	0
T61	0	3	0	0
T88	7719	35	0	0
T102	29478	3	0	0
T104	0	3	0	0
T127	8390	0	0	0
T128	0	47	0	0
T137	0	10	0	0
T140	0	15	0	0
T157	0	10	0	0
T158	0	10	0	0
T159	0	15	0	0
T160	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Unreachable
1	1	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	134974715	125	0	0
CgEnOn_A	134974715	125	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134974715	125	0	0
T3	485292	0	0	0
T21	0	1	0	0
T23	13384	0	0	0
T27	920	0	0	0
T29	1746	1	0	0
T30	1073	6	0	0
T31	0	2	0	0
T32	1967	0	0	0
T39	0	2	0	0
T55	2529	0	0	0
T88	749	0	0	0
T102	3040	0	0	0
T127	849	0	0	0
T137	0	2	0	0
T140	0	3	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134974715	125	0	0
T3	485292	0	0	0
T21	0	1	0	0
T23	13384	0	0	0
T27	920	0	0	0
T29	1746	1	0	0
T30	1073	6	0	0
T31	0	2	0	0
T32	1967	0	0	0
T39	0	2	0	0
T55	2529	0	0	0
T88	749	0	0	0
T102	3040	0	0	0
T127	849	0	0	0
T137	0	2	0	0
T140	0	3	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Unreachable
1	1	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	67486935	125	0	0
CgEnOn_A	67486935	125	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67486935	125	0	0
T3	242645	0	0	0
T21	0	1	0	0
T23	6693	0	0	0
T27	460	0	0	0
T29	873	1	0	0
T30	536	6	0	0
T31	0	2	0	0
T32	983	0	0	0
T39	0	2	0	0
T55	1265	0	0	0
T88	374	0	0	0
T102	1520	0	0	0
T127	424	0	0	0
T137	0	2	0	0
T140	0	3	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67486935	125	0	0
T3	242645	0	0	0
T21	0	1	0	0
T23	6693	0	0	0
T27	460	0	0	0
T29	873	1	0	0
T30	536	6	0	0
T31	0	2	0	0
T32	983	0	0	0
T39	0	2	0	0
T55	1265	0	0	0
T88	374	0	0	0
T102	1520	0	0	0
T127	424	0	0	0
T137	0	2	0	0
T140	0	3	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Unreachable
1	1	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	67486935	125	0	0
CgEnOn_A	67486935	125	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67486935	125	0	0
T3	242645	0	0	0
T21	0	1	0	0
T23	6693	0	0	0
T27	460	0	0	0
T29	873	1	0	0
T30	536	6	0	0
T31	0	2	0	0
T32	983	0	0	0
T39	0	2	0	0
T55	1265	0	0	0
T88	374	0	0	0
T102	1520	0	0	0
T127	424	0	0	0
T137	0	2	0	0
T140	0	3	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67486935	125	0	0
T3	242645	0	0	0
T21	0	1	0	0
T23	6693	0	0	0
T27	460	0	0	0
T29	873	1	0	0
T30	536	6	0	0
T31	0	2	0	0
T32	983	0	0	0
T39	0	2	0	0
T55	1265	0	0	0
T88	374	0	0	0
T102	1520	0	0	0
T127	424	0	0	0
T137	0	2	0	0
T140	0	3	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Unreachable
1	1	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	67486935	125	0	0
CgEnOn_A	67486935	125	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67486935	125	0	0
T3	242645	0	0	0
T21	0	1	0	0
T23	6693	0	0	0
T27	460	0	0	0
T29	873	1	0	0
T30	536	6	0	0
T31	0	2	0	0
T32	983	0	0	0
T39	0	2	0	0
T55	1265	0	0	0
T88	374	0	0	0
T102	1520	0	0	0
T127	424	0	0	0
T137	0	2	0	0
T140	0	3	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67486935	125	0	0
T3	242645	0	0	0
T21	0	1	0	0
T23	6693	0	0	0
T27	460	0	0	0
T29	873	1	0	0
T30	536	6	0	0
T31	0	2	0	0
T32	983	0	0	0
T39	0	2	0	0
T55	1265	0	0	0
T88	374	0	0	0
T102	1520	0	0	0
T127	424	0	0	0
T137	0	2	0	0
T140	0	3	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Unreachable
1	1	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	271333812	125	0	0
CgEnOn_A	271333812	121	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	271333812	125	0	0
T3	971316	0	0	0
T21	0	1	0	0
T23	51308	0	0	0
T27	1906	0	0	0
T29	3599	1	0	0
T30	2211	6	0	0
T31	0	2	0	0
T32	4000	0	0	0
T39	0	2	0	0
T55	5152	0	0	0
T88	1632	0	0	0
T102	6105	0	0	0
T127	1749	0	0	0
T137	0	2	0	0
T140	0	3	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	271333812	121	0	0
T3	971316	0	0	0
T23	51308	0	0	0
T27	1906	0	0	0
T29	3599	1	0	0
T30	2211	6	0	0
T31	0	2	0	0
T32	4000	0	0	0
T39	0	2	0	0
T55	5152	0	0	0
T88	1632	0	0	0
T102	6105	0	0	0
T127	1749	0	0	0
T137	0	2	0	0
T140	0	3	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	0	3	0	0
T160	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Unreachable
1	1	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	288270747	121	0	0
CgEnOn_A	288270747	120	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	288270747	121	0	0
T3	107782	0	0	0
T23	53447	0	0	0
T27	1985	0	0	0
T29	3712	3	0	0
T30	2393	6	0	0
T31	0	2	0	0
T32	4167	0	0	0
T40	0	1	0	0
T55	5366	0	0	0
T88	1700	0	0	0
T102	6360	0	0	0
T127	1823	0	0	0
T137	0	1	0	0
T140	0	4	0	0
T157	0	1	0	0
T158	0	3	0	0
T159	0	2	0	0
T160	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	288270747	120	0	0
T3	107782	0	0	0
T23	53447	0	0	0
T27	1985	0	0	0
T29	3712	3	0	0
T30	2393	6	0	0
T31	0	2	0	0
T32	4167	0	0	0
T40	0	1	0	0
T55	5366	0	0	0
T88	1700	0	0	0
T102	6360	0	0	0
T127	1823	0	0	0
T137	0	1	0	0
T140	0	4	0	0
T157	0	1	0	0
T158	0	3	0	0
T159	0	2	0	0
T160	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Unreachable
1	1	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	288270747	121	0	0
CgEnOn_A	288270747	120	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	288270747	121	0	0
T3	107782	0	0	0
T23	53447	0	0	0
T27	1985	0	0	0
T29	3712	3	0	0
T30	2393	6	0	0
T31	0	2	0	0
T32	4167	0	0	0
T40	0	1	0	0
T55	5366	0	0	0
T88	1700	0	0	0
T102	6360	0	0	0
T127	1823	0	0	0
T137	0	1	0	0
T140	0	4	0	0
T157	0	1	0	0
T158	0	3	0	0
T159	0	2	0	0
T160	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	288270747	120	0	0
T3	107782	0	0	0
T23	53447	0	0	0
T27	1985	0	0	0
T29	3712	3	0	0
T30	2393	6	0	0
T31	0	2	0	0
T32	4167	0	0	0
T40	0	1	0	0
T55	5366	0	0	0
T88	1700	0	0	0
T102	6360	0	0	0
T127	1823	0	0	0
T137	0	1	0	0
T140	0	4	0	0
T157	0	1	0	0
T158	0	3	0	0
T159	0	2	0	0
T160	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Unreachable
1	1	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	138403624	127	0	0
CgEnOn_A	138403624	127	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138403624	127	0	0
T3	508722	0	0	0
T23	25655	0	0	0
T27	953	0	0	0
T29	1826	1	0	0
T30	1156	4	0	0
T31	0	3	0	0
T32	2000	0	0	0
T40	0	1	0	0
T55	2576	0	0	0
T88	816	0	0	0
T102	3053	0	0	0
T127	874	0	0	0
T137	0	1	0	0
T140	0	3	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	0	2	0	0
T160	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138403624	127	0	0
T3	508722	0	0	0
T23	25655	0	0	0
T27	953	0	0	0
T29	1826	1	0	0
T30	1156	4	0	0
T31	0	3	0	0
T32	2000	0	0	0
T40	0	1	0	0
T55	2576	0	0	0
T88	816	0	0	0
T102	3053	0	0	0
T127	874	0	0	0
T137	0	1	0	0
T140	0	3	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	0	2	0	0
T160	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	67486935	5159	0	0
CgEnOn_A	67486935	2951	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67486935	5159	0	0
T1	505308	227	0	0
T2	22032	1	0	0
T4	16872	19	0	0
T5	1737	1	0	0
T15	1031	1	0	0
T16	505	1	0	0
T17	554	1	0	0
T18	26374	1	0	0
T19	1803	1	0	0
T20	575	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	67486935	2951	0	0
T1	505308	217	0	0
T2	22032	0	0	0
T3	0	47	0	0
T4	16872	0	0	0
T5	1737	0	0	0
T15	1031	0	0	0
T16	505	0	0	0
T17	554	0	0	0
T18	26374	0	0	0
T19	1803	0	0	0
T20	575	0	0	0
T29	0	1	0	0
T30	0	6	0	0
T31	0	2	0	0
T32	0	1	0	0
T88	0	12	0	0
T102	0	1	0	0
T104	0	1	0	0
T128	0	17	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	134974715	5193	0	0
CgEnOn_A	134974715	2985	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134974715	5193	0	0
T1	101062	229	0	0
T2	44064	1	0	0
T4	33742	19	0	0
T5	3474	1	0	0
T15	2063	1	0	0
T16	1014	1	0	0
T17	1108	1	0	0
T18	52747	1	0	0
T19	3606	1	0	0
T20	1152	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134974715	2985	0	0
T1	101062	219	0	0
T2	44064	0	0	0
T3	0	45	0	0
T4	33742	0	0	0
T5	3474	0	0	0
T15	2063	0	0	0
T16	1014	0	0	0
T17	1108	0	0	0
T18	52747	0	0	0
T19	3606	0	0	0
T20	1152	0	0	0
T29	0	1	0	0
T30	0	6	0	0
T31	0	2	0	0
T32	0	1	0	0
T88	0	12	0	0
T102	0	1	0	0
T104	0	1	0	0
T128	0	15	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	271333812	5201	0	0
CgEnOn_A	271333812	2989	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	271333812	5201	0	0
T1	201746	228	0	0
T2	88263	1	0	0
T4	124139	19	0	0
T5	7055	1	0	0
T15	4001	1	0	0
T16	2096	1	0	0
T17	2294	1	0	0
T18	105519	1	0	0
T19	7305	1	0	0
T20	2289	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	271333812	2989	0	0
T1	201746	218	0	0
T2	88263	0	0	0
T3	0	45	0	0
T4	124139	0	0	0
T5	7055	0	0	0
T15	4001	0	0	0
T16	2096	0	0	0
T17	2294	0	0	0
T18	105519	0	0	0
T19	7305	0	0	0
T20	2289	0	0	0
T29	0	1	0	0
T30	0	6	0	0
T31	0	2	0	0
T32	0	1	0	0
T88	0	11	0	0
T102	0	1	0	0
T104	0	1	0	0
T128	0	15	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	138403624	5202	0	0
CgEnOn_A	138403624	2990	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138403624	5202	0	0
T1	102231	238	0	0
T2	44133	1	0	0
T4	62072	19	0	0
T5	3527	1	0	0
T15	2001	1	0	0
T16	1048	1	0	0
T17	1147	1	0	0
T18	58521	1	0	0
T19	3652	1	0	0
T20	1145	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	138403624	2990	0	0
T1	102231	228	0	0
T2	44133	0	0	0
T3	0	44	0	0
T4	62072	0	0	0
T5	3527	0	0	0
T15	2001	0	0	0
T16	1048	0	0	0
T17	1147	0	0	0
T18	58521	0	0	0
T19	3652	0	0	0
T20	1145	0	0	0
T29	0	1	0	0
T30	0	4	0	0
T31	0	3	0	0
T32	0	1	0	0
T88	0	13	0	0
T102	0	1	0	0
T104	0	1	0	0
T128	0	15	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Covered	T1,T5,T19
1	1	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	288270747	2338	0	0
CgEnOn_A	288270747	2337	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	288270747	2338	0	0
T1	212979	87	0	0
T2	91944	0	0	0
T3	0	15	0	0
T4	129315	0	0	0
T5	7349	4	0	0
T15	4168	0	0	0
T16	2184	0	0	0
T17	2390	0	0	0
T18	145919	0	0	0
T19	7609	3	0	0
T20	2384	0	0	0
T29	0	3	0	0
T30	0	6	0	0
T55	0	1	0	0
T61	0	3	0	0
T83	0	8	0	0
T84	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	288270747	2337	0	0
T1	212979	87	0	0
T2	91944	0	0	0
T3	0	15	0	0
T4	129315	0	0	0
T5	7349	4	0	0
T15	4168	0	0	0
T16	2184	0	0	0
T17	2390	0	0	0
T18	145919	0	0	0
T19	7609	3	0	0
T20	2384	0	0	0
T29	0	3	0	0
T30	0	6	0	0
T55	0	1	0	0
T61	0	3	0	0
T83	0	8	0	0
T84	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Covered	T1,T5,T19
1	1	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	288270747	2358	0	0
CgEnOn_A	288270747	2357	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	288270747	2358	0	0
T1	212979	93	0	0
T2	91944	0	0	0
T3	0	17	0	0
T4	129315	0	0	0
T5	7349	2	0	0
T15	4168	0	0	0
T16	2184	0	0	0
T17	2390	0	0	0
T18	145919	0	0	0
T19	7609	4	0	0
T20	2384	0	0	0
T29	0	3	0	0
T30	0	6	0	0
T32	0	1	0	0
T61	0	4	0	0
T83	0	8	0	0
T102	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	288270747	2357	0	0
T1	212979	93	0	0
T2	91944	0	0	0
T3	0	17	0	0
T4	129315	0	0	0
T5	7349	2	0	0
T15	4168	0	0	0
T16	2184	0	0	0
T17	2390	0	0	0
T18	145919	0	0	0
T19	7609	4	0	0
T20	2384	0	0	0
T29	0	3	0	0
T30	0	6	0	0
T32	0	1	0	0
T61	0	4	0	0
T83	0	8	0	0
T102	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Covered	T1,T5,T19
1	1	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	288270747	2487	0	0
CgEnOn_A	288270747	2486	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	288270747	2487	0	0
T1	212979	100	0	0
T2	91944	0	0	0
T3	0	17	0	0
T4	129315	0	0	0
T5	7349	4	0	0
T15	4168	0	0	0
T16	2184	0	0	0
T17	2390	0	0	0
T18	145919	0	0	0
T19	7609	5	0	0
T20	2384	0	0	0
T29	0	3	0	0
T30	0	6	0	0
T32	0	1	0	0
T61	0	4	0	0
T83	0	8	0	0
T84	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	288270747	2486	0	0
T1	212979	100	0	0
T2	91944	0	0	0
T3	0	17	0	0
T4	129315	0	0	0
T5	7349	4	0	0
T15	4168	0	0	0
T16	2184	0	0	0
T17	2390	0	0	0
T18	145919	0	0	0
T19	7609	5	0	0
T20	2384	0	0	0
T29	0	3	0	0
T30	0	6	0	0
T32	0	1	0	0
T61	0	4	0	0
T83	0	8	0	0
T84	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T6
1	0	Covered	T1,T5,T19
1	1	Covered	T1,T5,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	288270747	2388	0	0
CgEnOn_A	288270747	2387	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	288270747	2388	0	0
T1	212979	91	0	0
T2	91944	0	0	0
T3	0	12	0	0
T4	129315	0	0	0
T5	7349	5	0	0
T15	4168	0	0	0
T16	2184	0	0	0
T17	2390	0	0	0
T18	145919	0	0	0
T19	7609	2	0	0
T20	2384	0	0	0
T29	0	3	0	0
T30	0	6	0	0
T32	0	1	0	0
T61	0	3	0	0
T83	0	8	0	0
T84	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	288270747	2387	0	0
T1	212979	91	0	0
T2	91944	0	0	0
T3	0	12	0	0
T4	129315	0	0	0
T5	7349	5	0	0
T15	4168	0	0	0
T16	2184	0	0	0
T17	2390	0	0	0
T18	145919	0	0	0
T19	7609	2	0	0
T20	2384	0	0	0
T29	0	3	0	0
T30	0	6	0	0
T32	0	1	0	0
T61	0	3	0	0
T83	0	8	0	0
T84	0	2	0	0