Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	274426	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1174966

1

T6

7

T1

68

T5

139

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	379078	1			T6	5		T1	18		T5	77
values[0x0]	495198	1			T6	8		T1	54		T5	111
values[0x1]	575116	1			T6	3		T1	74		T5	131

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	167464	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1281928

1

T6

7

T1

92

T5

184

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5166	1			T20	2		T39	1		T119	1
valid_sources[0x01]	5013	1			T5	3		T20	2		T89	2
valid_sources[0x02]	5116	1			T5	3		T2	1		T153	1
valid_sources[0x03]	5744	1			T1	1		T5	3		T3	2
valid_sources[0x04]	6083	1			T2	1		T39	3		T26	2
valid_sources[0x05]	6031	1			T5	1		T9	14		T10	1
valid_sources[0x06]	6051	1			T1	1		T119	2		T32	2
valid_sources[0x07]	5644	1			T5	2		T3	1		T26	1
valid_sources[0x08]	5160	1			T5	4		T31	2		T119	1
valid_sources[0x09]	5227	1			T1	1		T5	1		T3	1
valid_sources[0x0a]	5317	1			T2	5		T3	1		T26	3
valid_sources[0x0b]	5211	1			T1	1		T30	1		T39	1
valid_sources[0x0c]	5722	1			T5	8		T26	2		T21	1
valid_sources[0x0d]	5049	1			T2	1		T32	1		T9	8
valid_sources[0x0e]	6406	1			T1	2		T24	3		T21	1
valid_sources[0x0f]	5092	1			T5	1		T3	2		T120	9
valid_sources[0x10]	5910	1			T19	22		T39	2		T153	1
valid_sources[0x11]	6064	1			T5	1		T24	20		T119	1
valid_sources[0x12]	5846	1			T3	1		T21	1		T9	11
valid_sources[0x13]	5605	1			T2	2		T3	1		T26	1
valid_sources[0x14]	5910	1			T1	1		T5	1		T19	4
valid_sources[0x15]	5701	1			T1	1		T26	1		T21	1
valid_sources[0x16]	5731	1			T5	3		T2	1		T39	1
valid_sources[0x17]	5014	1			T5	1		T29	13		T30	1
valid_sources[0x18]	5211	1			T5	4		T119	1		T21	3
valid_sources[0x19]	5772	1			T5	2		T39	1		T119	1
valid_sources[0x1a]	5135	1			T25	2		T30	1		T153	1
valid_sources[0x1b]	5389	1			T1	1		T5	1		T89	1
valid_sources[0x1c]	6349	1			T1	3		T2	3		T9	7
valid_sources[0x1d]	5137	1			T39	1		T3	1		T26	1
valid_sources[0x1e]	4800	1			T5	2		T119	1		T21	1
valid_sources[0x1f]	6049	1			T1	1		T5	1		T89	1
valid_sources[0x20]	6151	1			T2	3		T3	1		T119	1
valid_sources[0x21]	6145	1			T1	2		T5	2		T24	15
valid_sources[0x22]	5655	1			T5	1		T20	5		T24	1
valid_sources[0x23]	6552	1			T1	3		T3	1		T9	7
valid_sources[0x24]	6136	1			T1	1		T2	2		T3	2
valid_sources[0x25]	5425	1			T2	2		T39	1		T9	17
valid_sources[0x26]	5057	1			T1	1		T20	9		T8	350
valid_sources[0x27]	5802	1			T5	3		T89	4		T3	1
valid_sources[0x28]	5166	1			T5	3		T2	5		T19	4
valid_sources[0x29]	5189	1			T1	1		T32	2		T9	7
valid_sources[0x2a]	5191	1			T5	1		T31	2		T153	1
valid_sources[0x2b]	5519	1			T26	2		T21	2		T9	3
valid_sources[0x2c]	5314	1			T1	1		T5	1		T2	5
valid_sources[0x2d]	5780	1			T5	3		T3	2		T119	2
valid_sources[0x2e]	5461	1			T2	5		T19	21		T26	1
valid_sources[0x2f]	5611	1			T5	5		T39	1		T32	2
valid_sources[0x30]	6063	1			T5	6		T2	5		T26	1
valid_sources[0x31]	8225	1			T1	2		T2	3		T3	1
valid_sources[0x32]	5928	1			T1	2		T5	2		T89	2
valid_sources[0x33]	5809	1			T5	1		T89	5		T3	1
valid_sources[0x34]	5670	1			T1	1		T5	2		T2	1
valid_sources[0x35]	6346	1			T5	1		T2	2		T29	4
valid_sources[0x36]	5563	1			T19	5		T20	2		T21	2
valid_sources[0x37]	5476	1			T25	1		T3	1		T119	1
valid_sources[0x38]	5755	1			T3	1		T26	1		T32	1
valid_sources[0x39]	5565	1			T3	1		T119	2		T153	1
valid_sources[0x3a]	6272	1			T2	7		T3	4		T26	1
valid_sources[0x3b]	5423	1			T9	4		T10	1		T11	244
valid_sources[0x3c]	5897	1			T39	1		T3	2		T119	1
valid_sources[0x3d]	5257	1			T1	4		T39	1		T3	1
valid_sources[0x3e]	6282	1			T1	1		T3	1		T119	1
valid_sources[0x3f]	5485	1			T5	4		T2	1		T31	3
valid_sources[0x40]	5647	1			T2	8		T17	7		T89	2
valid_sources[0x41]	5553	1			T5	6		T26	2		T9	6
valid_sources[0x42]	5724	1			T3	4		T9	6		T10	7
valid_sources[0x43]	5246	1			T1	1		T5	1		T24	10
valid_sources[0x44]	6043	1			T1	1		T5	1		T19	28
valid_sources[0x45]	5184	1			T1	1		T39	1		T3	1
valid_sources[0x46]	5473	1			T1	1		T19	2		T3	1
valid_sources[0x47]	6510	1			T1	1		T24	41		T89	1
valid_sources[0x48]	6117	1			T89	1		T39	2		T26	1
valid_sources[0x49]	5524	1			T1	1		T5	1		T89	1
valid_sources[0x4a]	5526	1			T89	1		T30	1		T3	1
valid_sources[0x4b]	6179	1			T1	1		T5	4		T119	1
valid_sources[0x4c]	6686	1			T1	1		T5	6		T2	2
valid_sources[0x4d]	5662	1			T1	1		T5	6		T2	1
valid_sources[0x4e]	4892	1			T1	1		T39	1		T26	2
valid_sources[0x4f]	5674	1			T1	2		T89	2		T3	1
valid_sources[0x50]	5986	1			T1	3		T5	1		T119	2
valid_sources[0x51]	5307	1			T39	1		T119	2		T32	1
valid_sources[0x52]	5588	1			T1	2		T119	1		T9	8
valid_sources[0x53]	5712	1			T1	4		T5	1		T30	1
valid_sources[0x54]	5413	1			T39	2		T119	1		T26	3
valid_sources[0x55]	5233	1			T2	1		T3	1		T119	1
valid_sources[0x56]	5928	1			T89	3		T9	11		T10	2
valid_sources[0x57]	6226	1			T5	1		T32	1		T9	7
valid_sources[0x58]	5880	1			T5	2		T3	1		T26	3
valid_sources[0x59]	5526	1			T1	2		T32	1		T153	1
valid_sources[0x5a]	5556	1			T5	3		T26	1		T21	3
valid_sources[0x5b]	5846	1			T1	1		T2	3		T19	30
valid_sources[0x5c]	5730	1			T5	1		T24	5		T3	1
valid_sources[0x5d]	6113	1			T1	2		T21	2		T9	10
valid_sources[0x5e]	5184	1			T4	66		T89	1		T3	1
valid_sources[0x5f]	6347	1			T21	3		T9	8		T10	5
valid_sources[0x60]	5384	1			T39	1		T119	1		T26	1
valid_sources[0x61]	5875	1			T19	20		T119	1		T21	1
valid_sources[0x62]	5477	1			T5	3		T19	8		T20	1
valid_sources[0x63]	5160	1			T1	2		T5	2		T89	1
valid_sources[0x64]	6062	1			T1	1		T3	1		T26	1
valid_sources[0x65]	6968	1			T5	4		T24	6		T9	6
valid_sources[0x66]	4925	1			T1	1		T5	1		T3	1
valid_sources[0x67]	6019	1			T5	3		T89	1		T3	1
valid_sources[0x68]	5408	1			T3	1		T26	2		T21	1
valid_sources[0x69]	5575	1			T1	1		T5	1		T89	2
valid_sources[0x6a]	5370	1			T5	1		T20	12		T89	1
valid_sources[0x6b]	5521	1			T5	5		T21	1		T9	5
valid_sources[0x6c]	5532	1			T1	1		T2	2		T17	6
valid_sources[0x6d]	5652	1			T2	1		T20	5		T30	1
valid_sources[0x6e]	5731	1			T1	1		T2	9		T39	2
valid_sources[0x6f]	5314	1			T1	1		T5	1		T19	3
valid_sources[0x70]	7642	1			T1	2		T5	1		T9	6
valid_sources[0x71]	5198	1			T5	6		T19	7		T21	2
valid_sources[0x72]	5522	1			T1	2		T3	1		T21	1
valid_sources[0x73]	5442	1			T1	1		T5	1		T24	25
valid_sources[0x74]	5625	1			T1	2		T39	5		T26	1
valid_sources[0x75]	5631	1			T1	1		T5	2		T21	1
valid_sources[0x76]	5915	1			T5	2		T2	5		T4	26
valid_sources[0x77]	5568	1			T30	1		T31	4		T3	1
valid_sources[0x78]	5861	1			T1	1		T5	2		T30	1
valid_sources[0x79]	4926	1			T1	1		T5	2		T17	13
valid_sources[0x7a]	5272	1			T26	1		T21	1		T9	9
valid_sources[0x7b]	5347	1			T5	1		T2	9		T24	17
valid_sources[0x7c]	5350	1			T5	1		T32	1		T9	7
valid_sources[0x7d]	5489	1			T5	3		T2	4		T89	2
valid_sources[0x7e]	5655	1			T5	2		T2	3		T89	1
valid_sources[0x7f]	4882	1			T1	1		T119	1		T26	1
valid_sources[0x80]	5059	1			T1	1		T5	1		T2	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

305535

1

T6

3

T1

11

T5

40

values[0x0]

all_enables

biggest_size

447016

1

T6

4

T1

33

T5

60

values[0x1]

all_enables

biggest_size

422415

1

T1

24

T5

39

T2

40