Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T15,T4,T20
0	1	Covered	T5,T15,T25
1	0	Covered	T6,T1,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T15,T4
1	0	Covered	T36,T37,T38
1	1	Covered	T6,T1,T5

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	619327869	7593	0	0
GateOpen_A	619327869	12977	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619327869	7593	0	0
T4	52172	0	0	0
T9	0	56	0	0
T10	0	48	0	0
T15	3400	33	0	0
T16	7511	0	0	0
T17	5093	0	0	0
T18	16395	0	0	0
T19	407365	0	0	0
T20	3663	2	0	0
T22	0	3	0	0
T24	413017	0	0	0
T25	2690	0	0	0
T36	0	4	0	0
T37	0	26	0	0
T40	0	4	0	0
T89	15281	0	0	0
T104	0	1	0	0
T146	0	13	0	0
T153	0	37	0	0
T183	0	11	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	619327869	12977	0	0
T4	52172	20	0	0
T9	0	43	0	0
T15	3400	33	0	0
T16	7511	0	0	0
T17	5093	0	0	0
T18	16395	4	0	0
T19	407365	0	0	0
T20	3663	2	0	0
T24	413017	0	0	0
T25	2690	4	0	0
T29	0	4	0	0
T32	0	4	0	0
T89	15281	4	0	0
T119	0	4	0	0
T153	0	41	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T15,T4,T153
0	1	Covered	T5,T15,T25
1	0	Covered	T6,T1,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T15,T4
1	0	Covered	T36,T37,T38
1	1	Covered	T6,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	68341955	1817	0	0
GateOpen_A	68341955	3163	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68341955	1817	0	0
T4	3785	0	0	0
T9	0	11	0	0
T10	0	11	0	0
T15	374	7	0	0
T16	824	0	0	0
T17	579	0	0	0
T18	1804	0	0	0
T19	43640	0	0	0
T20	403	0	0	0
T22	0	1	0	0
T24	42357	0	0	0
T25	288	0	0	0
T36	0	1	0	0
T37	0	7	0	0
T40	0	1	0	0
T89	1676	0	0	0
T146	0	3	0	0
T153	0	8	0	0
T183	0	6	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68341955	3163	0	0
T4	3785	5	0	0
T9	0	19	0	0
T15	374	7	0	0
T16	824	0	0	0
T17	579	0	0	0
T18	1804	1	0	0
T19	43640	0	0	0
T20	403	0	0	0
T24	42357	0	0	0
T25	288	1	0	0
T29	0	1	0	0
T32	0	1	0	0
T89	1676	1	0	0
T119	0	1	0	0
T153	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T15,T4,T20
0	1	Covered	T5,T15,T25
1	0	Covered	T6,T1,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T15,T4
1	0	Covered	T36,T37,T38
1	1	Covered	T6,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	136684253	1926	0	0
GateOpen_A	136684253	3272	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	136684253	1926	0	0
T4	7568	0	0	0
T9	0	15	0	0
T10	0	11	0	0
T15	747	9	0	0
T16	1647	0	0	0
T17	1158	0	0	0
T18	3608	0	0	0
T19	87280	0	0	0
T20	806	1	0	0
T22	0	1	0	0
T24	84714	0	0	0
T25	576	0	0	0
T36	0	1	0	0
T37	0	7	0	0
T40	0	1	0	0
T89	3351	0	0	0
T146	0	4	0	0
T153	0	9	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	136684253	3272	0	0
T4	7568	5	0	0
T15	747	9	0	0
T16	1647	0	0	0
T17	1158	0	0	0
T18	3608	1	0	0
T19	87280	0	0	0
T20	806	1	0	0
T24	84714	0	0	0
T25	576	1	0	0
T29	0	1	0	0
T32	0	1	0	0
T89	3351	1	0	0
T119	0	1	0	0
T153	0	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T15,T4,T20
0	1	Covered	T5,T15,T25
1	0	Covered	T6,T1,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T15,T4
1	0	Covered	T36,T37,T38
1	1	Covered	T6,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	274513161	1926	0	0
GateOpen_A	274513161	3272	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	274513161	1926	0	0
T4	27212	0	0	0
T9	0	14	0	0
T10	0	13	0	0
T15	1519	9	0	0
T16	3360	0	0	0
T17	2237	0	0	0
T18	7322	0	0	0
T19	174694	0	0	0
T20	1636	1	0	0
T24	169507	0	0	0
T25	1218	0	0	0
T36	0	1	0	0
T37	0	7	0	0
T40	0	1	0	0
T89	6836	0	0	0
T104	0	1	0	0
T146	0	3	0	0
T153	0	9	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	274513161	3272	0	0
T4	27212	5	0	0
T15	1519	9	0	0
T16	3360	0	0	0
T17	2237	0	0	0
T18	7322	1	0	0
T19	174694	0	0	0
T20	1636	1	0	0
T24	169507	0	0	0
T25	1218	1	0	0
T29	0	1	0	0
T32	0	1	0	0
T89	6836	1	0	0
T119	0	1	0	0
T153	0	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T15,T4,T153
0	1	Covered	T5,T15,T25
1	0	Covered	T6,T1,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T15,T4
1	0	Covered	T36,T37,T38
1	1	Covered	T6,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	139788500	1924	0	0
GateOpen_A	139788500	3270	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139788500	1924	0	0
T4	13607	0	0	0
T9	0	16	0	0
T10	0	13	0	0
T15	760	8	0	0
T16	1680	0	0	0
T17	1119	0	0	0
T18	3661	0	0	0
T19	101751	0	0	0
T20	818	0	0	0
T22	0	1	0	0
T24	116439	0	0	0
T25	608	0	0	0
T36	0	1	0	0
T37	0	5	0	0
T40	0	1	0	0
T89	3418	0	0	0
T146	0	3	0	0
T153	0	11	0	0
T183	0	5	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139788500	3270	0	0
T4	13607	5	0	0
T9	0	24	0	0
T15	760	8	0	0
T16	1680	0	0	0
T17	1119	0	0	0
T18	3661	1	0	0
T19	101751	0	0	0
T20	818	0	0	0
T24	116439	0	0	0
T25	608	1	0	0
T29	0	1	0	0
T32	0	1	0	0
T89	3418	1	0	0
T119	0	1	0	0
T153	0	12	0	0