Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	292338660	33137	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292338660	33137	0	0
T1	324520	109	0	0
T2	622065	223	0	0
T3	0	34	0	0
T4	141730	0	0	0
T5	115590	0	0	0
T8	0	124	0	0
T9	0	438	0	0
T10	0	201	0	0
T11	0	366	0	0
T12	0	450	0	0
T13	0	201	0	0
T14	0	1271	0	0
T15	7755	0	0	0
T16	8745	0	0	0
T17	11645	0	0	0
T18	9530	0	0	0
T19	1103850	0	0	0
T20	8175	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	58467732	5062	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58467732	5062	0	0
T1	64904	14	0	0
T2	124413	30	0	0
T3	0	6	0	0
T4	28346	0	0	0
T5	23118	0	0	0
T8	0	19	0	0
T9	0	58	0	0
T10	0	26	0	0
T11	0	60	0	0
T12	0	63	0	0
T13	0	33	0	0
T14	0	243	0	0
T15	1551	0	0	0
T16	1749	0	0	0
T17	2329	0	0	0
T18	1906	0	0	0
T19	220770	0	0	0
T20	1635	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	58467732	5023	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58467732	5023	0	0
T1	64904	14	0	0
T2	124413	29	0	0
T3	0	6	0	0
T4	28346	0	0	0
T5	23118	0	0	0
T8	0	18	0	0
T9	0	57	0	0
T10	0	29	0	0
T11	0	59	0	0
T12	0	63	0	0
T13	0	31	0	0
T14	0	243	0	0
T15	1551	0	0	0
T16	1749	0	0	0
T17	2329	0	0	0
T18	1906	0	0	0
T19	220770	0	0	0
T20	1635	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	58467732	6614	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58467732	6614	0	0
T1	64904	21	0	0
T2	124413	45	0	0
T3	0	6	0	0
T4	28346	0	0	0
T5	23118	0	0	0
T8	0	25	0	0
T9	0	89	0	0
T10	0	39	0	0
T11	0	73	0	0
T12	0	90	0	0
T13	0	41	0	0
T14	0	243	0	0
T15	1551	0	0	0
T16	1749	0	0	0
T17	2329	0	0	0
T18	1906	0	0	0
T19	220770	0	0	0
T20	1635	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	58467732	6608	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58467732	6608	0	0
T1	64904	22	0	0
T2	124413	46	0	0
T3	0	7	0	0
T4	28346	0	0	0
T5	23118	0	0	0
T8	0	25	0	0
T9	0	88	0	0
T10	0	42	0	0
T11	0	73	0	0
T12	0	91	0	0
T13	0	39	0	0
T14	0	243	0	0
T15	1551	0	0	0
T16	1749	0	0	0
T17	2329	0	0	0
T18	1906	0	0	0
T19	220770	0	0	0
T20	1635	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	58467732	9830	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58467732	9830	0	0
T1	64904	38	0	0
T2	124413	73	0	0
T3	0	9	0	0
T4	28346	0	0	0
T5	23118	0	0	0
T8	0	37	0	0
T9	0	146	0	0
T10	0	65	0	0
T11	0	101	0	0
T12	0	143	0	0
T13	0	57	0	0
T14	0	299	0	0
T15	1551	0	0	0
T16	1749	0	0	0
T17	2329	0	0	0
T18	1906	0	0	0
T19	220770	0	0	0
T20	1635	0	0	0