Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T5
0	1	Unreachable
1	0	Covered	T5,T4,T9

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	58467732	56645157	0	0
AllClkBypReqTrue_A	58467732	63505	0	0
IoClkBypReqFalse_A	58467732	56598406	0	2313
IoClkBypReqTrue_A	58467732	106442	0	0
LcClkBypAckFalse_A	58467732	56647376	0	0
LcClkBypAckTrue_A	58467732	61286	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58467732	56645157	0	0
T1	64904	64783	0	0
T2	124413	124304	0	0
T4	28346	2162	0	0
T5	23118	23044	0	0
T6	1143	1117	0	0
T15	1551	1426	0	0
T16	1749	1663	0	0
T17	2329	2095	0	0
T18	1906	1852	0	0
T19	220770	220607	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58467732	63505	0	0
T1	64904	0	0	0
T2	124413	0	0	0
T4	28346	0	0	0
T5	23118	0	0	0
T6	1143	10	0	0
T9	0	119	0	0
T10	0	468	0	0
T15	1551	0	0	0
T16	1749	0	0	0
T17	2329	50	0	0
T18	1906	0	0	0
T19	220770	0	0	0
T29	0	197	0	0
T39	0	127	0	0
T90	0	213	0	0
T114	0	34	0	0
T115	0	8	0	0
T116	0	323	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58467732	56598406	0	2313
T1	64904	64781	0	3
T2	124413	124302	0	3
T4	28346	2152	0	3
T5	23118	23038	0	3
T6	1143	1066	0	3
T15	1551	1424	0	3
T16	1749	1661	0	3
T17	2329	1961	0	3
T18	1906	1850	0	3
T19	220770	220605	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58467732	106442	0	0
T1	64904	0	0	0
T2	124413	0	0	0
T4	28346	0	0	0
T5	23118	0	0	0
T6	1143	59	0	0
T9	0	321	0	0
T10	0	739	0	0
T15	1551	0	0	0
T16	1749	0	0	0
T17	2329	182	0	0
T18	1906	0	0	0
T19	220770	0	0	0
T29	0	337	0	0
T39	0	69	0	0
T90	0	469	0	0
T114	0	48	0	0
T116	0	435	0	0
T117	0	57	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58467732	56647376	0	0
T1	64904	64783	0	0
T2	124413	124304	0	0
T4	28346	2162	0	0
T5	23118	23044	0	0
T6	1143	1105	0	0
T15	1551	1426	0	0
T16	1749	1663	0	0
T17	2329	2110	0	0
T18	1906	1852	0	0
T19	220770	220607	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58467732	61286	0	0
T1	64904	0	0	0
T2	124413	0	0	0
T4	28346	0	0	0
T5	23118	0	0	0
T6	1143	22	0	0
T9	0	171	0	0
T10	0	555	0	0
T15	1551	0	0	0
T16	1749	0	0	0
T17	2329	35	0	0
T18	1906	0	0	0
T19	220770	0	0	0
T29	0	109	0	0
T39	0	66	0	0
T90	0	197	0	0
T116	0	271	0	0
T117	0	4	0	0
T118	0	30	0	0