Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1163706940	8341	0	0
TransStop_A	1163706940	4297	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1163706940	8341	0	0
T2	513028	0	0	0
T4	113388	0	0	0
T5	553980	36	0	0
T9	0	176	0	0
T10	0	4	0	0
T15	6328	0	0	0
T16	14000	19	0	0
T17	9320	0	0	0
T18	30512	17	0	0
T19	823908	0	0	0
T20	6816	4	0	0
T24	898304	0	0	0
T40	0	4	0	0
T89	0	33	0	0
T119	0	29	0	0
T120	0	11	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1163706940	4297	0	0
T2	513028	0	0	0
T4	113388	0	0	0
T5	553980	24	0	0
T9	0	98	0	0
T10	0	4	0	0
T15	6328	0	0	0
T16	14000	8	0	0
T17	9320	0	0	0
T18	30512	3	0	0
T19	823908	0	0	0
T20	6816	4	0	0
T24	898304	0	0	0
T40	0	4	0	0
T89	0	15	0	0
T119	0	19	0	0
T120	0	2	0	0
T121	0	2	0	0
T122	0	11	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	290926735	2123	0	0
TransStop_A	290926735	1065	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290926735	2123	0	0
T2	128257	0	0	0
T4	28347	0	0	0
T5	138495	7	0	0
T9	0	45	0	0
T10	0	1	0	0
T15	1582	0	0	0
T16	3500	4	0	0
T17	2330	0	0	0
T18	7628	3	0	0
T19	205977	0	0	0
T20	1704	1	0	0
T24	224576	0	0	0
T40	0	1	0	0
T89	0	11	0	0
T119	0	9	0	0
T120	0	2	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290926735	1065	0	0
T2	128257	0	0	0
T4	28347	0	0	0
T5	138495	5	0	0
T9	0	27	0	0
T10	0	1	0	0
T15	1582	0	0	0
T16	3500	3	0	0
T17	2330	0	0	0
T18	7628	0	0	0
T19	205977	0	0	0
T20	1704	1	0	0
T24	224576	0	0	0
T40	0	1	0	0
T89	0	5	0	0
T119	0	6	0	0
T121	0	1	0	0
T122	0	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	290926735	2088	0	0
TransStop_A	290926735	1096	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290926735	2088	0	0
T2	128257	0	0	0
T4	28347	0	0	0
T5	138495	7	0	0
T9	0	42	0	0
T10	0	1	0	0
T15	1582	0	0	0
T16	3500	5	0	0
T17	2330	0	0	0
T18	7628	3	0	0
T19	205977	0	0	0
T20	1704	1	0	0
T24	224576	0	0	0
T40	0	1	0	0
T89	0	5	0	0
T119	0	5	0	0
T120	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290926735	1096	0	0
T2	128257	0	0	0
T4	28347	0	0	0
T5	138495	6	0	0
T9	0	22	0	0
T10	0	1	0	0
T15	1582	0	0	0
T16	3500	2	0	0
T17	2330	0	0	0
T18	7628	0	0	0
T19	205977	0	0	0
T20	1704	1	0	0
T24	224576	0	0	0
T40	0	1	0	0
T89	0	3	0	0
T119	0	4	0	0
T121	0	1	0	0
T122	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	290926735	2042	0	0
TransStop_A	290926735	1048	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290926735	2042	0	0
T2	128257	0	0	0
T4	28347	0	0	0
T5	138495	10	0	0
T9	0	40	0	0
T10	0	1	0	0
T15	1582	0	0	0
T16	3500	4	0	0
T17	2330	0	0	0
T18	7628	5	0	0
T19	205977	0	0	0
T20	1704	1	0	0
T24	224576	0	0	0
T40	0	1	0	0
T89	0	7	0	0
T119	0	7	0	0
T120	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290926735	1048	0	0
T2	128257	0	0	0
T4	28347	0	0	0
T5	138495	6	0	0
T9	0	22	0	0
T10	0	1	0	0
T15	1582	0	0	0
T16	3500	1	0	0
T17	2330	0	0	0
T18	7628	1	0	0
T19	205977	0	0	0
T20	1704	1	0	0
T24	224576	0	0	0
T40	0	1	0	0
T89	0	2	0	0
T119	0	4	0	0
T120	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	290926735	2088	0	0
TransStop_A	290926735	1088	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290926735	2088	0	0
T2	128257	0	0	0
T4	28347	0	0	0
T5	138495	12	0	0
T9	0	49	0	0
T10	0	1	0	0
T15	1582	0	0	0
T16	3500	6	0	0
T17	2330	0	0	0
T18	7628	6	0	0
T19	205977	0	0	0
T20	1704	1	0	0
T24	224576	0	0	0
T40	0	1	0	0
T89	0	10	0	0
T119	0	8	0	0
T120	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290926735	1088	0	0
T2	128257	0	0	0
T4	28347	0	0	0
T5	138495	7	0	0
T9	0	27	0	0
T10	0	1	0	0
T15	1582	0	0	0
T16	3500	2	0	0
T17	2330	0	0	0
T18	7628	2	0	0
T19	205977	0	0	0
T20	1704	1	0	0
T24	224576	0	0	0
T40	0	1	0	0
T89	0	5	0	0
T119	0	5	0	0
T120	0	1	0	0