Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	58467732	6251761	0	55

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58467732	6251761	0	55
T1	64904	12715	0	1
T2	124413	24565	0	1
T3	0	2853	0	1
T4	28346	0	0	0
T5	23118	0	0	0
T8	0	12588	0	1
T9	0	47908	0	0
T10	0	24641	0	0
T11	0	830222	0	0
T12	0	44229	0	1
T15	1551	0	0	0
T16	1749	0	0	0
T17	2329	0	0	0
T18	1906	0	0	0
T19	220770	0	0	0
T20	1635	0	0	0
T21	0	1338	0	1
T22	0	1813	0	1
T23	0	0	0	1
T82	0	0	0	1
T123	0	0	0	1