Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	59576302	1624778	0	0
clk_enables_rd_A	59576302	10316	0	0
clk_hints_rd_A	59576302	9418	0	0
extclk_ctrl_rd_A	59576302	9492	0	0
extclk_ctrl_regwen_rd_A	59576302	7357	0	0
jitter_enable_rd_A	59576302	14111	0	0
jitter_regwen_rd_A	59576302	7422	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59576302	1624778	0	0
T11	158461	79402	0	0
T14	0	142199	0	0
T28	0	77246	0	0
T33	0	187021	0	0
T66	0	25274	0	0
T67	0	130429	0	0
T68	0	54998	0	0
T69	0	60687	0	0
T70	0	23899	0	0
T71	0	195962	0	0
T72	1612	0	0	0
T73	2658	0	0	0
T74	1673	0	0	0
T75	2428	0	0	0
T76	1373	0	0	0
T77	1424	0	0	0
T78	1804	0	0	0
T79	1677	0	0	0
T80	73729	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59576302	10316	0	0
T9	579499	5	0	0
T10	328619	1	0	0
T36	860	0	0	0
T40	1018	0	0	0
T66	0	1081	0	0
T68	0	1139	0	0
T105	10733	0	0	0
T114	1400	0	0	0
T115	1315	0	0	0
T121	1443	0	0	0
T139	0	3	0	0
T140	0	9	0	0
T141	0	2	0	0
T142	0	8	0	0
T143	0	3	0	0
T144	0	5	0	0
T145	1401	0	0	0
T146	1146	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59576302	9418	0	0
T9	579499	7	0	0
T10	328619	0	0	0
T13	0	5	0	0
T36	860	0	0	0
T40	1018	0	0	0
T66	0	844	0	0
T105	10733	0	0	0
T114	1400	0	0	0
T115	1315	0	0	0
T121	1443	0	0	0
T139	0	7	0	0
T140	0	1	0	0
T141	0	5	0	0
T142	0	1	0	0
T143	0	10	0	0
T144	0	6	0	0
T145	1401	0	0	0
T146	1146	0	0	0
T147	0	3	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59576302	9492	0	0
T3	13922	0	0	0
T8	86561	0	0	0
T9	0	33	0	0
T10	0	34	0	0
T13	0	77	0	0
T21	124401	0	0	0
T26	62125	0	0	0
T27	11055	0	0	0
T32	1784	0	0	0
T39	2429	41	0	0
T79	0	40	0	0
T119	2126	0	0	0
T120	1883	0	0	0
T148	0	10	0	0
T149	0	6	0	0
T150	0	13	0	0
T151	0	26	0	0
T152	0	1	0	0
T153	1810	0	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59576302	7357	0	0
T46	0	5	0	0
T66	863023	771	0	0
T68	0	966	0	0
T102	0	23	0	0
T154	0	31	0	0
T155	0	32	0	0
T156	0	10	0	0
T157	0	41	0	0
T158	0	11	0	0
T159	0	3	0	0
T160	1903	0	0	0
T161	3666	0	0	0
T162	19413	0	0	0
T163	1613	0	0	0
T164	2326	0	0	0
T165	1760	0	0	0
T166	831	0	0	0
T167	930	0	0	0
T168	189918	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59576302	14111	0	0
T9	579499	336	0	0
T10	328619	67	0	0
T13	0	45	0	0
T36	860	0	0	0
T40	1018	0	0	0
T66	0	1319	0	0
T105	10733	0	0	0
T114	1400	0	0	0
T115	1315	0	0	0
T121	1443	0	0	0
T139	0	145	0	0
T140	0	226	0	0
T141	0	94	0	0
T142	0	354	0	0
T145	1401	0	0	0
T146	1146	0	0	0
T147	0	113	0	0
T169	0	69	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	59576302	7422	0	0
T66	863023	845	0	0
T68	0	1048	0	0
T84	0	54	0	0
T85	0	9	0	0
T108	0	21	0	0
T160	1903	0	0	0
T161	3666	0	0	0
T162	19413	0	0	0
T163	1613	0	0	0
T164	2326	0	0	0
T165	1760	0	0	0
T166	831	0	0	0
T167	930	0	0	0
T168	189918	0	0	0
T170	0	1401	0	0
T171	0	1	0	0
T172	0	463	0	0
T173	0	2	0	0
T174	0	19	0	0