Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	175403196	448	0	0
StatusRise_A	175403196	448	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175403196	448	0	0
T10	985857	0	0	0
T36	2580	3	0	0
T37	0	17	0	0
T38	0	8	0	0
T40	3054	0	0	0
T105	32199	0	0	0
T114	4200	0	0	0
T115	3945	0	0	0
T121	4329	0	0	0
T122	9111	0	0	0
T145	4203	0	0	0
T146	3438	0	0	0
T176	0	8	0	0
T177	0	10	0	0
T178	0	14	0	0
T179	0	6	0	0
T180	0	6	0	0
T181	0	9	0	0
T182	0	8	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	175403196	448	0	0
T10	985857	0	0	0
T36	2580	3	0	0
T37	0	17	0	0
T38	0	8	0	0
T40	3054	0	0	0
T105	32199	0	0	0
T114	4200	0	0	0
T115	3945	0	0	0
T121	4329	0	0	0
T122	9111	0	0	0
T145	4203	0	0	0
T146	3438	0	0	0
T176	0	8	0	0
T177	0	10	0	0
T178	0	14	0	0
T179	0	6	0	0
T180	0	6	0	0
T181	0	9	0	0
T182	0	8	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	58467732	146	0	0
StatusRise_A	58467732	146	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58467732	146	0	0
T10	328619	0	0	0
T36	860	1	0	0
T37	0	5	0	0
T38	0	3	0	0
T40	1018	0	0	0
T105	10733	0	0	0
T114	1400	0	0	0
T115	1315	0	0	0
T121	1443	0	0	0
T122	3037	0	0	0
T145	1401	0	0	0
T146	1146	0	0	0
T176	0	2	0	0
T177	0	3	0	0
T178	0	4	0	0
T179	0	2	0	0
T180	0	2	0	0
T181	0	3	0	0
T182	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58467732	146	0	0
T10	328619	0	0	0
T36	860	1	0	0
T37	0	5	0	0
T38	0	3	0	0
T40	1018	0	0	0
T105	10733	0	0	0
T114	1400	0	0	0
T115	1315	0	0	0
T121	1443	0	0	0
T122	3037	0	0	0
T145	1401	0	0	0
T146	1146	0	0	0
T176	0	2	0	0
T177	0	3	0	0
T178	0	4	0	0
T179	0	2	0	0
T180	0	2	0	0
T181	0	3	0	0
T182	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	58467732	154	0	0
StatusRise_A	58467732	154	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58467732	154	0	0
T10	328619	0	0	0
T36	860	1	0	0
T37	0	7	0	0
T38	0	3	0	0
T40	1018	0	0	0
T105	10733	0	0	0
T114	1400	0	0	0
T115	1315	0	0	0
T121	1443	0	0	0
T122	3037	0	0	0
T145	1401	0	0	0
T146	1146	0	0	0
T176	0	4	0	0
T177	0	3	0	0
T178	0	5	0	0
T179	0	2	0	0
T180	0	3	0	0
T181	0	3	0	0
T182	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58467732	154	0	0
T10	328619	0	0	0
T36	860	1	0	0
T37	0	7	0	0
T38	0	3	0	0
T40	1018	0	0	0
T105	10733	0	0	0
T114	1400	0	0	0
T115	1315	0	0	0
T121	1443	0	0	0
T122	3037	0	0	0
T145	1401	0	0	0
T146	1146	0	0	0
T176	0	4	0	0
T177	0	3	0	0
T178	0	5	0	0
T179	0	2	0	0
T180	0	3	0	0
T181	0	3	0	0
T182	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	58467732	148	0	0
StatusRise_A	58467732	148	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58467732	148	0	0
T10	328619	0	0	0
T36	860	1	0	0
T37	0	5	0	0
T38	0	2	0	0
T40	1018	0	0	0
T105	10733	0	0	0
T114	1400	0	0	0
T115	1315	0	0	0
T121	1443	0	0	0
T122	3037	0	0	0
T145	1401	0	0	0
T146	1146	0	0	0
T176	0	2	0	0
T177	0	4	0	0
T178	0	5	0	0
T179	0	2	0	0
T180	0	1	0	0
T181	0	3	0	0
T182	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58467732	148	0	0
T10	328619	0	0	0
T36	860	1	0	0
T37	0	5	0	0
T38	0	2	0	0
T40	1018	0	0	0
T105	10733	0	0	0
T114	1400	0	0	0
T115	1315	0	0	0
T121	1443	0	0	0
T122	3037	0	0	0
T145	1401	0	0	0
T146	1146	0	0	0
T176	0	2	0	0
T177	0	4	0	0
T178	0	5	0	0
T179	0	2	0	0
T180	0	1	0	0
T181	0	3	0	0
T182	0	3	0	0