Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T9
1	0	Covered	T6,T1,T5
1	1	Covered	T6,T1,T5

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	29165	0	0
CgEnOn_A	2147483647	21538	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	29165	0	0
T1	114719	3	0	0
T2	343672	3	0	0
T4	66910	15	0	0
T5	340757	16	0	0
T6	12214	3	0	0
T10	580648	0	0	0
T15	4220	46	0	0
T16	9328	7	0	0
T17	6301	3	0	0
T18	20360	6	0	0
T19	511590	3	0	0
T20	1703	1	0	0
T36	3621	6	0	0
T37	0	35	0	0
T38	0	15	0	0
T40	9022	0	0	0
T105	92975	0	0	0
T114	2924	0	0	0
T115	2878	0	0	0
T121	6410	0	0	0
T122	38537	0	0	0
T145	16756	0	0	0
T146	10190	0	0	0
T176	0	20	0	0
T177	0	15	0	0
T178	0	25	0	0
T179	0	10	0	0
T180	0	15	0	0
T181	0	15	0	0
T182	0	15	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	21538	0	0
T4	66910	0	0	0
T5	138494	7	0	0
T9	0	106	0	0
T10	580648	55	0	0
T15	4220	43	0	0
T16	9328	0	0	0
T17	6301	0	0	0
T18	20360	0	0	0
T19	511590	0	0	0
T20	4546	3	0	0
T22	0	1	0	0
T24	521154	0	0	0
T25	2082	8	0	0
T36	3621	9	0	0
T37	0	49	0	0
T38	0	15	0	0
T40	9022	4	0	0
T89	11860	0	0	0
T104	0	1	0	0
T105	92975	0	0	0
T114	2924	0	0	0
T115	2878	0	0	0
T121	6410	0	0	0
T122	38537	0	0	0
T145	16756	0	0	0
T146	10190	16	0	0
T153	0	34	0	0
T176	0	20	0	0
T177	0	15	0	0
T178	0	25	0	0
T179	0	10	0	0
T180	0	15	0	0
T181	0	15	0	0
T182	0	15	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T9
1	0	Unreachable
1	1	Covered	T6,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	136683880	155	0	0
CgEnOn_A	136683880	155	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	136683880	155	0	0
T10	129115	0	0	0
T36	784	1	0	0
T37	0	7	0	0
T38	0	3	0	0
T40	1978	0	0	0
T105	20647	0	0	0
T114	632	0	0	0
T115	620	0	0	0
T121	1410	0	0	0
T122	8552	0	0	0
T145	3712	0	0	0
T146	2241	0	0	0
T176	0	4	0	0
T177	0	3	0	0
T178	0	5	0	0
T179	0	2	0	0
T180	0	3	0	0
T181	0	3	0	0
T182	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	136683880	155	0	0
T10	129115	0	0	0
T36	784	1	0	0
T37	0	7	0	0
T38	0	3	0	0
T40	1978	0	0	0
T105	20647	0	0	0
T114	632	0	0	0
T115	620	0	0	0
T121	1410	0	0	0
T122	8552	0	0	0
T145	3712	0	0	0
T146	2241	0	0	0
T176	0	4	0	0
T177	0	3	0	0
T178	0	5	0	0
T179	0	2	0	0
T180	0	3	0	0
T181	0	3	0	0
T182	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T9
1	0	Unreachable
1	1	Covered	T6,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	68341574	155	0	0
CgEnOn_A	68341574	155	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68341574	155	0	0
T10	64555	0	0	0
T36	392	1	0	0
T37	0	7	0	0
T38	0	3	0	0
T40	989	0	0	0
T105	10323	0	0	0
T114	316	0	0	0
T115	310	0	0	0
T121	705	0	0	0
T122	4276	0	0	0
T145	1856	0	0	0
T146	1120	0	0	0
T176	0	4	0	0
T177	0	3	0	0
T178	0	5	0	0
T179	0	2	0	0
T180	0	3	0	0
T181	0	3	0	0
T182	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68341574	155	0	0
T10	64555	0	0	0
T36	392	1	0	0
T37	0	7	0	0
T38	0	3	0	0
T40	989	0	0	0
T105	10323	0	0	0
T114	316	0	0	0
T115	310	0	0	0
T121	705	0	0	0
T122	4276	0	0	0
T145	1856	0	0	0
T146	1120	0	0	0
T176	0	4	0	0
T177	0	3	0	0
T178	0	5	0	0
T179	0	2	0	0
T180	0	3	0	0
T181	0	3	0	0
T182	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T9
1	0	Unreachable
1	1	Covered	T6,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	68341574	155	0	0
CgEnOn_A	68341574	155	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68341574	155	0	0
T10	64555	0	0	0
T36	392	1	0	0
T37	0	7	0	0
T38	0	3	0	0
T40	989	0	0	0
T105	10323	0	0	0
T114	316	0	0	0
T115	310	0	0	0
T121	705	0	0	0
T122	4276	0	0	0
T145	1856	0	0	0
T146	1120	0	0	0
T176	0	4	0	0
T177	0	3	0	0
T178	0	5	0	0
T179	0	2	0	0
T180	0	3	0	0
T181	0	3	0	0
T182	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68341574	155	0	0
T10	64555	0	0	0
T36	392	1	0	0
T37	0	7	0	0
T38	0	3	0	0
T40	989	0	0	0
T105	10323	0	0	0
T114	316	0	0	0
T115	310	0	0	0
T121	705	0	0	0
T122	4276	0	0	0
T145	1856	0	0	0
T146	1120	0	0	0
T176	0	4	0	0
T177	0	3	0	0
T178	0	5	0	0
T179	0	2	0	0
T180	0	3	0	0
T181	0	3	0	0
T182	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T9
1	0	Unreachable
1	1	Covered	T6,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	68341574	155	0	0
CgEnOn_A	68341574	155	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68341574	155	0	0
T10	64555	0	0	0
T36	392	1	0	0
T37	0	7	0	0
T38	0	3	0	0
T40	989	0	0	0
T105	10323	0	0	0
T114	316	0	0	0
T115	310	0	0	0
T121	705	0	0	0
T122	4276	0	0	0
T145	1856	0	0	0
T146	1120	0	0	0
T176	0	4	0	0
T177	0	3	0	0
T178	0	5	0	0
T179	0	2	0	0
T180	0	3	0	0
T181	0	3	0	0
T182	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68341574	155	0	0
T10	64555	0	0	0
T36	392	1	0	0
T37	0	7	0	0
T38	0	3	0	0
T40	989	0	0	0
T105	10323	0	0	0
T114	316	0	0	0
T115	310	0	0	0
T121	705	0	0	0
T122	4276	0	0	0
T145	1856	0	0	0
T146	1120	0	0	0
T176	0	4	0	0
T177	0	3	0	0
T178	0	5	0	0
T179	0	2	0	0
T180	0	3	0	0
T181	0	3	0	0
T182	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T9
1	0	Unreachable
1	1	Covered	T6,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	274512764	155	0	0
CgEnOn_A	274512764	154	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	274512764	155	0	0
T10	257868	0	0	0
T36	1661	1	0	0
T37	0	7	0	0
T38	0	3	0	0
T40	4077	0	0	0
T105	41359	0	0	0
T114	1344	0	0	0
T115	1328	0	0	0
T121	2885	0	0	0
T122	17157	0	0	0
T145	7476	0	0	0
T146	4589	0	0	0
T176	0	4	0	0
T177	0	3	0	0
T178	0	5	0	0
T179	0	2	0	0
T180	0	3	0	0
T181	0	3	0	0
T182	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	274512764	154	0	0
T10	257868	0	0	0
T36	1661	1	0	0
T37	0	7	0	0
T38	0	3	0	0
T40	4077	0	0	0
T105	41359	0	0	0
T114	1344	0	0	0
T115	1328	0	0	0
T121	2885	0	0	0
T122	17157	0	0	0
T145	7476	0	0	0
T146	4589	0	0	0
T176	0	4	0	0
T177	0	3	0	0
T178	0	5	0	0
T179	0	2	0	0
T180	0	3	0	0
T181	0	3	0	0
T182	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T9
1	0	Unreachable
1	1	Covered	T6,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	290926322	146	0	0
CgEnOn_A	290926322	146	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290926322	146	0	0
T10	316619	0	0	0
T36	1760	1	0	0
T37	0	5	0	0
T38	0	3	0	0
T40	4248	0	0	0
T105	67084	0	0	0
T114	1400	0	0	0
T115	1383	0	0	0
T121	3005	0	0	0
T122	17873	0	0	0
T145	7788	0	0	0
T146	4780	0	0	0
T176	0	2	0	0
T177	0	3	0	0
T178	0	4	0	0
T179	0	2	0	0
T180	0	2	0	0
T181	0	3	0	0
T182	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290926322	146	0	0
T10	316619	0	0	0
T36	1760	1	0	0
T37	0	5	0	0
T38	0	3	0	0
T40	4248	0	0	0
T105	67084	0	0	0
T114	1400	0	0	0
T115	1383	0	0	0
T121	3005	0	0	0
T122	17873	0	0	0
T145	7788	0	0	0
T146	4780	0	0	0
T176	0	2	0	0
T177	0	3	0	0
T178	0	4	0	0
T179	0	2	0	0
T180	0	2	0	0
T181	0	3	0	0
T182	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T9
1	0	Unreachable
1	1	Covered	T6,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	290926322	146	0	0
CgEnOn_A	290926322	146	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290926322	146	0	0
T10	316619	0	0	0
T36	1760	1	0	0
T37	0	5	0	0
T38	0	3	0	0
T40	4248	0	0	0
T105	67084	0	0	0
T114	1400	0	0	0
T115	1383	0	0	0
T121	3005	0	0	0
T122	17873	0	0	0
T145	7788	0	0	0
T146	4780	0	0	0
T176	0	2	0	0
T177	0	3	0	0
T178	0	4	0	0
T179	0	2	0	0
T180	0	2	0	0
T181	0	3	0	0
T182	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290926322	146	0	0
T10	316619	0	0	0
T36	1760	1	0	0
T37	0	5	0	0
T38	0	3	0	0
T40	4248	0	0	0
T105	67084	0	0	0
T114	1400	0	0	0
T115	1383	0	0	0
T121	3005	0	0	0
T122	17873	0	0	0
T145	7788	0	0	0
T146	4780	0	0	0
T176	0	2	0	0
T177	0	3	0	0
T178	0	4	0	0
T179	0	2	0	0
T180	0	2	0	0
T181	0	3	0	0
T182	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T9
1	0	Unreachable
1	1	Covered	T6,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	139788084	148	0	0
CgEnOn_A	139788084	148	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139788084	148	0	0
T10	151979	0	0	0
T36	851	1	0	0
T37	0	5	0	0
T38	0	2	0	0
T40	2038	0	0	0
T105	32201	0	0	0
T114	672	0	0	0
T115	664	0	0	0
T121	1443	0	0	0
T122	8579	0	0	0
T145	3738	0	0	0
T146	2294	0	0	0
T176	0	2	0	0
T177	0	4	0	0
T178	0	5	0	0
T179	0	2	0	0
T180	0	1	0	0
T181	0	3	0	0
T182	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139788084	148	0	0
T10	151979	0	0	0
T36	851	1	0	0
T37	0	5	0	0
T38	0	2	0	0
T40	2038	0	0	0
T105	32201	0	0	0
T114	672	0	0	0
T115	664	0	0	0
T121	1443	0	0	0
T122	8579	0	0	0
T145	3738	0	0	0
T146	2294	0	0	0
T176	0	2	0	0
T177	0	4	0	0
T178	0	5	0	0
T179	0	2	0	0
T180	0	1	0	0
T181	0	3	0	0
T182	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T6,T1,T5
1	1	Covered	T6,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	68341574	4757	0	0
CgEnOn_A	68341574	2851	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68341574	4757	0	0
T1	16379	1	0	0
T2	30764	1	0	0
T4	3784	5	0	0
T5	28863	3	0	0
T6	1784	1	0	0
T15	373	15	0	0
T16	823	1	0	0
T17	578	1	0	0
T18	1804	1	0	0
T19	43640	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68341574	2851	0	0
T4	3784	0	0	0
T9	0	17	0	0
T10	0	19	0	0
T15	373	14	0	0
T16	823	0	0	0
T17	578	0	0	0
T18	1804	0	0	0
T19	43640	0	0	0
T20	403	0	0	0
T22	0	1	0	0
T24	42357	0	0	0
T25	288	3	0	0
T36	0	1	0	0
T37	0	7	0	0
T40	0	1	0	0
T89	1675	0	0	0
T146	0	6	0	0
T153	0	11	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T6,T1,T5
1	1	Covered	T6,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	136683880	4755	0	0
CgEnOn_A	136683880	2849	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	136683880	4755	0	0
T1	32758	1	0	0
T2	61528	1	0	0
T4	7568	5	0	0
T5	57729	3	0	0
T6	3568	1	0	0
T15	747	16	0	0
T16	1647	1	0	0
T17	1158	1	0	0
T18	3607	1	0	0
T19	87280	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	136683880	2849	0	0
T4	7568	0	0	0
T9	0	23	0	0
T10	0	18	0	0
T15	747	15	0	0
T16	1647	0	0	0
T17	1158	0	0	0
T18	3607	0	0	0
T19	87280	0	0	0
T20	805	1	0	0
T24	84714	0	0	0
T25	576	3	0	0
T36	0	1	0	0
T37	0	7	0	0
T40	0	1	0	0
T89	3350	0	0	0
T146	0	5	0	0
T153	0	12	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T6,T1,T5
1	1	Covered	T6,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	274512764	4761	0	0
CgEnOn_A	274512764	2854	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	274512764	4761	0	0
T1	65582	1	0	0
T2	123123	1	0	0
T4	27212	5	0	0
T5	115671	3	0	0
T6	6862	1	0	0
T15	1518	15	0	0
T16	3359	1	0	0
T17	2236	1	0	0
T18	7322	1	0	0
T19	174693	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	274512764	2854	0	0
T4	27212	0	0	0
T9	0	21	0	0
T10	0	18	0	0
T15	1518	14	0	0
T16	3359	0	0	0
T17	2236	0	0	0
T18	7322	0	0	0
T19	174693	0	0	0
T20	1635	1	0	0
T24	169507	0	0	0
T25	1218	2	0	0
T36	0	1	0	0
T40	0	1	0	0
T89	6835	0	0	0
T104	0	1	0	0
T146	0	5	0	0
T153	0	11	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T6,T1,T5
1	1	Covered	T6,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	139788084	4752	0	0
CgEnOn_A	139788084	2845	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139788084	4752	0	0
T1	32793	1	0	0
T2	61564	1	0	0
T4	13606	5	0	0
T5	63598	3	0	0
T6	3431	1	0	0
T15	759	16	0	0
T16	1680	1	0	0
T17	1118	1	0	0
T18	3661	1	0	0
T19	101750	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	139788084	2845	0	0
T4	13606	0	0	0
T9	0	23	0	0
T10	0	20	0	0
T15	759	15	0	0
T16	1680	0	0	0
T17	1118	0	0	0
T18	3661	0	0	0
T19	101750	0	0	0
T20	817	0	0	0
T22	0	1	0	0
T24	116438	0	0	0
T25	608	2	0	0
T36	0	1	0	0
T37	0	5	0	0
T40	0	1	0	0
T89	3418	0	0	0
T146	0	6	0	0
T153	0	12	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T9
1	0	Covered	T5,T16,T18
1	1	Covered	T6,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	290926322	2269	0	0
CgEnOn_A	290926322	2269	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290926322	2269	0	0
T2	128257	0	0	0
T4	28346	0	0	0
T5	138494	7	0	0
T9	0	45	0	0
T15	1582	0	0	0
T16	3499	4	0	0
T17	2329	0	0	0
T18	7627	3	0	0
T19	205977	0	0	0
T20	1703	1	0	0
T24	224576	0	0	0
T36	0	1	0	0
T40	0	1	0	0
T89	0	11	0	0
T119	0	9	0	0
T120	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290926322	2269	0	0
T2	128257	0	0	0
T4	28346	0	0	0
T5	138494	7	0	0
T9	0	45	0	0
T15	1582	0	0	0
T16	3499	4	0	0
T17	2329	0	0	0
T18	7627	3	0	0
T19	205977	0	0	0
T20	1703	1	0	0
T24	224576	0	0	0
T36	0	1	0	0
T40	0	1	0	0
T89	0	11	0	0
T119	0	9	0	0
T120	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T9
1	0	Covered	T5,T16,T18
1	1	Covered	T6,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	290926322	2234	0	0
CgEnOn_A	290926322	2234	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290926322	2234	0	0
T2	128257	0	0	0
T4	28346	0	0	0
T5	138494	7	0	0
T9	0	42	0	0
T15	1582	0	0	0
T16	3499	5	0	0
T17	2329	0	0	0
T18	7627	3	0	0
T19	205977	0	0	0
T20	1703	1	0	0
T24	224576	0	0	0
T36	0	1	0	0
T40	0	1	0	0
T89	0	5	0	0
T119	0	5	0	0
T120	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290926322	2234	0	0
T2	128257	0	0	0
T4	28346	0	0	0
T5	138494	7	0	0
T9	0	42	0	0
T15	1582	0	0	0
T16	3499	5	0	0
T17	2329	0	0	0
T18	7627	3	0	0
T19	205977	0	0	0
T20	1703	1	0	0
T24	224576	0	0	0
T36	0	1	0	0
T40	0	1	0	0
T89	0	5	0	0
T119	0	5	0	0
T120	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T9
1	0	Covered	T5,T16,T18
1	1	Covered	T6,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	290926322	2188	0	0
CgEnOn_A	290926322	2188	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290926322	2188	0	0
T2	128257	0	0	0
T4	28346	0	0	0
T5	138494	10	0	0
T9	0	40	0	0
T15	1582	0	0	0
T16	3499	4	0	0
T17	2329	0	0	0
T18	7627	5	0	0
T19	205977	0	0	0
T20	1703	1	0	0
T24	224576	0	0	0
T36	0	1	0	0
T40	0	1	0	0
T89	0	7	0	0
T119	0	7	0	0
T120	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290926322	2188	0	0
T2	128257	0	0	0
T4	28346	0	0	0
T5	138494	10	0	0
T9	0	40	0	0
T15	1582	0	0	0
T16	3499	4	0	0
T17	2329	0	0	0
T18	7627	5	0	0
T19	205977	0	0	0
T20	1703	1	0	0
T24	224576	0	0	0
T36	0	1	0	0
T40	0	1	0	0
T89	0	7	0	0
T119	0	7	0	0
T120	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T4,T9
1	0	Covered	T5,T16,T18
1	1	Covered	T6,T1,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	290926322	2234	0	0
CgEnOn_A	290926322	2234	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290926322	2234	0	0
T2	128257	0	0	0
T4	28346	0	0	0
T5	138494	12	0	0
T9	0	49	0	0
T15	1582	0	0	0
T16	3499	6	0	0
T17	2329	0	0	0
T18	7627	6	0	0
T19	205977	0	0	0
T20	1703	1	0	0
T24	224576	0	0	0
T36	0	1	0	0
T40	0	1	0	0
T89	0	10	0	0
T119	0	8	0	0
T120	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	290926322	2234	0	0
T2	128257	0	0	0
T4	28346	0	0	0
T5	138494	12	0	0
T9	0	49	0	0
T15	1582	0	0	0
T16	3499	6	0	0
T17	2329	0	0	0
T18	7627	6	0	0
T19	205977	0	0	0
T20	1703	1	0	0
T24	224576	0	0	0
T36	0	1	0	0
T40	0	1	0	0
T89	0	10	0	0
T119	0	8	0	0
T120	0	4	0	0