Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	353983	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1673738

1

T6

3

T25

16

T5

30

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	516176	1			T25	18		T5	3		T26	20
values[0x0]	698628	1			T6	3		T7	3		T25	18
values[0x1]	812917	1			T6	5		T25	19		T5	27

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	210577	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1817144

1

T6

4

T25

20

T5

36

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7979	1			T5	2		T26	25		T1	4
valid_sources[0x01]	7541	1			T1	1		T4	1		T35	2
valid_sources[0x02]	7371	1			T28	2		T4	4		T35	1
valid_sources[0x03]	8272	1			T28	3		T38	2		T3	14
valid_sources[0x04]	7915	1			T5	1		T1	9		T4	1
valid_sources[0x05]	7990	1			T1	1		T4	1		T35	1
valid_sources[0x06]	9155	1			T28	1		T1	8		T23	1
valid_sources[0x07]	8562	1			T5	6		T27	1		T1	10
valid_sources[0x08]	7422	1			T25	1		T5	1		T27	1
valid_sources[0x09]	9909	1			T5	1		T1	1		T4	3
valid_sources[0x0a]	7942	1			T4	2		T35	1		T126	1
valid_sources[0x0b]	8245	1			T1	16		T4	1		T33	1
valid_sources[0x0c]	7409	1			T5	1		T1	6		T4	1
valid_sources[0x0d]	7654	1			T1	7		T4	3		T123	3
valid_sources[0x0e]	7797	1			T28	1		T1	12		T4	1
valid_sources[0x0f]	8295	1			T1	3		T4	2		T124	1
valid_sources[0x10]	7605	1			T25	2		T27	2		T28	4
valid_sources[0x11]	7774	1			T4	2		T123	2		T126	1
valid_sources[0x12]	8538	1			T25	3		T27	1		T1	6
valid_sources[0x13]	7845	1			T38	1		T1	16		T4	4
valid_sources[0x14]	7251	1			T5	1		T1	3		T4	2
valid_sources[0x15]	7382	1			T28	1		T4	3		T3	8
valid_sources[0x16]	8284	1			T1	16		T4	2		T24	4
valid_sources[0x17]	8709	1			T38	1		T1	4		T4	7
valid_sources[0x18]	7710	1			T27	1		T28	1		T4	3
valid_sources[0x19]	7101	1			T27	1		T1	1		T35	1
valid_sources[0x1a]	7382	1			T38	1		T1	3		T4	1
valid_sources[0x1b]	7428	1			T28	1		T38	1		T1	2
valid_sources[0x1c]	7436	1			T28	1		T1	8		T4	5
valid_sources[0x1d]	7553	1			T1	6		T4	8		T123	2
valid_sources[0x1e]	8011	1			T1	1		T4	1		T35	2
valid_sources[0x1f]	7153	1			T27	1		T28	1		T1	3
valid_sources[0x20]	8353	1			T27	2		T38	1		T4	2
valid_sources[0x21]	7706	1			T1	8		T4	4		T35	1
valid_sources[0x22]	8072	1			T1	9		T4	1		T121	1
valid_sources[0x23]	7921	1			T27	1		T1	2		T4	8
valid_sources[0x24]	7945	1			T5	1		T1	16		T4	1
valid_sources[0x25]	8419	1			T28	1		T1	3		T20	1
valid_sources[0x26]	7844	1			T25	2		T28	1		T4	1
valid_sources[0x27]	8369	1			T27	1		T4	6		T35	1
valid_sources[0x28]	7807	1			T25	1		T28	1		T1	5
valid_sources[0x29]	8478	1			T1	1		T4	4		T3	8
valid_sources[0x2a]	8782	1			T1	2		T3	13		T11	4
valid_sources[0x2b]	7573	1			T1	8		T4	4		T80	7
valid_sources[0x2c]	8603	1			T28	3		T1	6		T35	1
valid_sources[0x2d]	8109	1			T4	3		T35	3		T36	9
valid_sources[0x2e]	6738	1			T27	1		T28	5		T1	7
valid_sources[0x2f]	8462	1			T27	1		T4	1		T123	1
valid_sources[0x30]	8314	1			T25	2		T5	2		T30	12
valid_sources[0x31]	7411	1			T28	1		T4	1		T35	2
valid_sources[0x32]	6573	1			T27	1		T1	9		T4	1
valid_sources[0x33]	9308	1			T1	2		T4	3		T3	11
valid_sources[0x34]	7965	1			T35	1		T123	1		T3	16
valid_sources[0x35]	7614	1			T6	8		T20	1		T4	4
valid_sources[0x36]	6720	1			T5	1		T4	1		T35	1
valid_sources[0x37]	8741	1			T28	1		T30	1		T1	9
valid_sources[0x38]	7892	1			T25	2		T1	11		T4	4
valid_sources[0x39]	8129	1			T25	1		T28	1		T4	4
valid_sources[0x3a]	7659	1			T1	1		T20	2		T3	8
valid_sources[0x3b]	8809	1			T1	7		T4	3		T23	1
valid_sources[0x3c]	8162	1			T27	1		T4	1		T35	1
valid_sources[0x3d]	8392	1			T27	1		T1	13		T4	3
valid_sources[0x3e]	7910	1			T4	3		T3	4		T11	2
valid_sources[0x3f]	8305	1			T1	3		T4	4		T35	2
valid_sources[0x40]	7675	1			T28	1		T38	1		T1	12
valid_sources[0x41]	7484	1			T1	24		T4	5		T35	3
valid_sources[0x42]	7112	1			T27	1		T1	4		T4	1
valid_sources[0x43]	7706	1			T1	2		T4	1		T35	1
valid_sources[0x44]	7542	1			T27	1		T4	6		T3	9
valid_sources[0x45]	8286	1			T25	3		T1	6		T4	2
valid_sources[0x46]	7512	1			T4	5		T23	1		T35	2
valid_sources[0x47]	7775	1			T30	10		T1	7		T123	3
valid_sources[0x48]	7767	1			T5	3		T30	3		T1	5
valid_sources[0x49]	7452	1			T1	7		T4	6		T124	1
valid_sources[0x4a]	8471	1			T1	2		T4	1		T35	2
valid_sources[0x4b]	8025	1			T1	1		T4	1		T35	1
valid_sources[0x4c]	8398	1			T5	2		T1	15		T4	1
valid_sources[0x4d]	7669	1			T1	1		T4	7		T35	1
valid_sources[0x4e]	8293	1			T28	1		T4	8		T35	1
valid_sources[0x4f]	8214	1			T5	2		T38	1		T1	2
valid_sources[0x50]	8290	1			T1	9		T4	1		T125	3
valid_sources[0x51]	7949	1			T28	1		T38	1		T4	3
valid_sources[0x52]	7918	1			T38	1		T4	2		T35	2
valid_sources[0x53]	7650	1			T27	1		T1	10		T4	5
valid_sources[0x54]	7097	1			T1	8		T23	1		T3	9
valid_sources[0x55]	7187	1			T27	1		T1	11		T20	2
valid_sources[0x56]	7500	1			T5	1		T1	3		T4	8
valid_sources[0x57]	8849	1			T1	2		T4	1		T24	1
valid_sources[0x58]	8113	1			T5	1		T4	2		T35	1
valid_sources[0x59]	7962	1			T1	1		T4	1		T24	1
valid_sources[0x5a]	8846	1			T1	7		T4	2		T3	9
valid_sources[0x5b]	7408	1			T5	3		T1	6		T4	1
valid_sources[0x5c]	8718	1			T5	1		T27	1		T38	1
valid_sources[0x5d]	7759	1			T28	1		T1	1		T4	7
valid_sources[0x5e]	8514	1			T3	5		T11	1		T13	10
valid_sources[0x5f]	8011	1			T4	1		T35	4		T3	13
valid_sources[0x60]	7884	1			T1	9		T4	1		T126	1
valid_sources[0x61]	8388	1			T27	1		T28	2		T1	1
valid_sources[0x62]	7790	1			T38	1		T1	3		T4	3
valid_sources[0x63]	7260	1			T27	4		T1	6		T4	2
valid_sources[0x64]	8029	1			T28	2		T1	7		T4	6
valid_sources[0x65]	7551	1			T1	5		T4	6		T123	2
valid_sources[0x66]	7707	1			T1	3		T4	3		T35	1
valid_sources[0x67]	8137	1			T4	1		T35	2		T127	2
valid_sources[0x68]	7138	1			T28	3		T1	1		T22	5
valid_sources[0x69]	8492	1			T1	2		T4	11		T35	1
valid_sources[0x6a]	7706	1			T1	5		T4	11		T3	5
valid_sources[0x6b]	7736	1			T1	3		T20	1		T4	6
valid_sources[0x6c]	7231	1			T4	1		T126	1		T3	3
valid_sources[0x6d]	8077	1			T4	3		T24	4		T35	1
valid_sources[0x6e]	7350	1			T1	6		T4	1		T121	1
valid_sources[0x6f]	7821	1			T5	1		T38	1		T1	6
valid_sources[0x70]	7788	1			T27	1		T28	1		T1	2
valid_sources[0x71]	7389	1			T1	8		T20	1		T4	3
valid_sources[0x72]	7924	1			T25	1		T5	1		T1	3
valid_sources[0x73]	8179	1			T28	2		T30	23		T38	1
valid_sources[0x74]	7883	1			T25	1		T1	2		T4	9
valid_sources[0x75]	6505	1			T26	1		T4	4		T80	4
valid_sources[0x76]	8064	1			T4	4		T35	3		T123	1
valid_sources[0x77]	7782	1			T5	1		T38	1		T1	1
valid_sources[0x78]	9195	1			T25	5		T5	1		T28	2
valid_sources[0x79]	8032	1			T30	3		T1	5		T4	1
valid_sources[0x7a]	7981	1			T5	2		T27	2		T38	2
valid_sources[0x7b]	7912	1			T5	1		T1	4		T4	2
valid_sources[0x7c]	7150	1			T27	1		T1	2		T4	3
valid_sources[0x7d]	6821	1			T25	3		T28	1		T1	6
valid_sources[0x7e]	9135	1			T4	6		T126	2		T3	13
valid_sources[0x7f]	7739	1			T28	1		T4	2		T36	1
valid_sources[0x80]	8262	1			T4	2		T35	1		T3	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

430485

1

T25

10

T5

1

T26

8

values[0x0]

all_enables

biggest_size

637533

1

T6

1

T25

5

T5

20

values[0x1]

all_enables

biggest_size

605720

1

T6

2

T25

1

T5

9