Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T28,T29
0	1	Covered	T7,T1,T20
1	0	Covered	T6,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T28,T29
1	0	Covered	T8,T37,T18
1	1	Covered	T6,T7,T8

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	761806835	8616	0	0
GateOpen_A	761806835	14607	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761806835	8616	0	0
T1	0	8	0	0
T5	82429	0	0	0
T8	2885	19	0	0
T18	0	9	0	0
T20	0	13	0	0
T25	8811	0	0	0
T26	10252	0	0	0
T27	5875	0	0	0
T28	16115	4	0	0
T29	9212	4	0	0
T30	10632	0	0	0
T37	3132	5	0	0
T38	15597	0	0	0
T39	0	21	0	0
T123	0	3	0	0
T155	0	1	0	0
T156	0	10	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761806835	14607	0	0
T5	82429	0	0	0
T6	7110	4	0	0
T7	2618	4	0	0
T8	2885	23	0	0
T25	8811	4	0	0
T26	10252	4	0	0
T27	5875	4	0	0
T28	16115	8	0	0
T29	9212	4	0	0
T30	10632	0	0	0
T37	0	9	0	0
T38	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T28,T29
0	1	Covered	T7,T1,T20
1	0	Covered	T6,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T28,T29
1	0	Covered	T8,T37,T18
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	84030579	2071	0	0
GateOpen_A	84030579	3568	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84030579	2071	0	0
T1	0	2	0	0
T5	8821	0	0	0
T8	298	5	0	0
T18	0	2	0	0
T20	0	2	0	0
T25	1006	0	0	0
T26	1203	0	0	0
T27	676	0	0	0
T28	1773	1	0	0
T29	1015	1	0	0
T30	1175	0	0	0
T37	335	1	0	0
T38	1795	0	0	0
T39	0	6	0	0
T123	0	1	0	0
T156	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84030579	3568	0	0
T5	8821	0	0	0
T6	770	1	0	0
T7	276	1	0	0
T8	298	6	0	0
T25	1006	1	0	0
T26	1203	1	0	0
T27	676	1	0	0
T28	1773	2	0	0
T29	1015	1	0	0
T30	1175	0	0	0
T37	0	2	0	0
T38	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T28,T29
0	1	Covered	T7,T1,T20
1	0	Covered	T6,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T28,T29
1	0	Covered	T8,T37,T18
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	168061732	2182	0	0
GateOpen_A	168061732	3679	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168061732	2182	0	0
T1	0	2	0	0
T5	17642	0	0	0
T8	596	5	0	0
T18	0	2	0	0
T20	0	4	0	0
T25	2015	0	0	0
T26	2407	0	0	0
T27	1353	0	0	0
T28	3546	1	0	0
T29	2030	1	0	0
T30	2350	0	0	0
T37	670	1	0	0
T38	3590	0	0	0
T39	0	5	0	0
T123	0	1	0	0
T156	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168061732	3679	0	0
T5	17642	0	0	0
T6	1540	1	0	0
T7	551	1	0	0
T8	596	6	0	0
T25	2015	1	0	0
T26	2407	1	0	0
T27	1353	1	0	0
T28	3546	2	0	0
T29	2030	1	0	0
T30	2350	0	0	0
T37	0	2	0	0
T38	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T28,T29
0	1	Covered	T7,T1,T20
1	0	Covered	T6,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T28,T29
1	0	Covered	T8,T37,T18
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	337456449	2191	0	0
GateOpen_A	337456449	3689	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337456449	2191	0	0
T1	0	2	0	0
T5	35390	0	0	0
T8	1298	5	0	0
T18	0	2	0	0
T20	0	3	0	0
T25	3860	0	0	0
T26	4428	0	0	0
T27	2564	0	0	0
T28	7197	1	0	0
T29	4111	1	0	0
T30	4738	0	0	0
T37	1445	1	0	0
T38	6808	0	0	0
T39	0	5	0	0
T123	0	1	0	0
T156	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337456449	3689	0	0
T5	35390	0	0	0
T6	3200	1	0	0
T7	1194	1	0	0
T8	1298	6	0	0
T25	3860	1	0	0
T26	4428	1	0	0
T27	2564	1	0	0
T28	7197	2	0	0
T29	4111	1	0	0
T30	4738	0	0	0
T37	0	2	0	0
T38	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T8,T28,T29
0	1	Covered	T7,T1,T20
1	0	Covered	T6,T7,T8

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T28,T29
1	0	Covered	T8,T37,T18
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	172258075	2172	0	0
GateOpen_A	172258075	3671	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172258075	2172	0	0
T1	0	2	0	0
T5	20576	0	0	0
T8	693	4	0	0
T18	0	3	0	0
T20	0	4	0	0
T25	1930	0	0	0
T26	2214	0	0	0
T27	1282	0	0	0
T28	3599	1	0	0
T29	2056	1	0	0
T30	2369	0	0	0
T37	682	2	0	0
T38	3404	0	0	0
T39	0	5	0	0
T155	0	1	0	0
T156	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172258075	3671	0	0
T5	20576	0	0	0
T6	1600	1	0	0
T7	597	1	0	0
T8	693	5	0	0
T25	1930	1	0	0
T26	2214	1	0	0
T27	1282	1	0	0
T28	3599	2	0	0
T29	2056	1	0	0
T30	2369	0	0	0
T37	0	3	0	0
T38	0	1	0	0