Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	459401420	43795	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	459401420	43795	0	0
T1	487040	57	0	0
T2	990995	418	0	0
T3	0	216	0	0
T4	419100	0	0	0
T11	0	97	0	0
T12	0	90	0	0
T13	0	1008	0	0
T14	0	214	0	0
T15	0	60	0	0
T16	0	755	0	0
T17	0	1175	0	0
T18	7535	0	0	0
T19	11980	0	0	0
T20	5575	0	0	0
T21	6200	0	0	0
T22	9555	0	0	0
T23	5170	0	0	0
T24	4580	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	91880284	6492	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91880284	6492	0	0
T1	97408	9	0	0
T2	198199	54	0	0
T3	0	29	0	0
T4	83820	0	0	0
T11	0	15	0	0
T12	0	13	0	0
T13	0	134	0	0
T14	0	29	0	0
T15	0	9	0	0
T16	0	110	0	0
T17	0	167	0	0
T18	1507	0	0	0
T19	2396	0	0	0
T20	1115	0	0	0
T21	1240	0	0	0
T22	1911	0	0	0
T23	1034	0	0	0
T24	916	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	91880284	6443	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91880284	6443	0	0
T1	97408	9	0	0
T2	198199	54	0	0
T3	0	28	0	0
T4	83820	0	0	0
T11	0	16	0	0
T12	0	11	0	0
T13	0	134	0	0
T14	0	28	0	0
T15	0	9	0	0
T16	0	108	0	0
T17	0	162	0	0
T18	1507	0	0	0
T19	2396	0	0	0
T20	1115	0	0	0
T21	1240	0	0	0
T22	1911	0	0	0
T23	1034	0	0	0
T24	916	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	91880284	8805	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91880284	8805	0	0
T1	97408	12	0	0
T2	198199	85	0	0
T3	0	46	0	0
T4	83820	0	0	0
T11	0	20	0	0
T12	0	18	0	0
T13	0	206	0	0
T14	0	42	0	0
T15	0	12	0	0
T16	0	150	0	0
T17	0	236	0	0
T18	1507	0	0	0
T19	2396	0	0	0
T20	1115	0	0	0
T21	1240	0	0	0
T22	1911	0	0	0
T23	1034	0	0	0
T24	916	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	91880284	8795	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91880284	8795	0	0
T1	97408	11	0	0
T2	198199	84	0	0
T3	0	43	0	0
T4	83820	0	0	0
T11	0	19	0	0
T12	0	18	0	0
T13	0	201	0	0
T14	0	42	0	0
T15	0	13	0	0
T16	0	152	0	0
T17	0	237	0	0
T18	1507	0	0	0
T19	2396	0	0	0
T20	1115	0	0	0
T21	1240	0	0	0
T22	1911	0	0	0
T23	1034	0	0	0
T24	916	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	91880284	13260	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91880284	13260	0	0
T1	97408	16	0	0
T2	198199	141	0	0
T3	0	70	0	0
T4	83820	0	0	0
T11	0	27	0	0
T12	0	30	0	0
T13	0	333	0	0
T14	0	73	0	0
T15	0	17	0	0
T16	0	235	0	0
T17	0	373	0	0
T18	1507	0	0	0
T19	2396	0	0	0
T20	1115	0	0	0
T21	1240	0	0	0
T22	1911	0	0	0
T23	1034	0	0	0
T24	916	0	0	0