Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Unreachable
1	0	Covered	T1,T4,T35

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	91880284	89719751	0	0
AllClkBypReqTrue_A	91880284	93136	0	0
IoClkBypReqFalse_A	91880284	89658425	0	2331
IoClkBypReqTrue_A	91880284	150272	0	0
LcClkBypAckFalse_A	91880284	89725433	0	0
LcClkBypAckTrue_A	91880284	87454	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91880284	89719751	0	0
T5	5144	5125	0	0
T6	832	786	0	0
T7	1169	969	0	0
T8	1527	1373	0	0
T25	1970	1809	0	0
T26	2214	2125	0	0
T27	2563	2206	0	0
T28	1873	1809	0	0
T29	2012	1965	0	0
T30	2418	2342	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91880284	93136	0	0
T1	97408	44	0	0
T5	5144	0	0	0
T22	0	101	0	0
T23	0	77	0	0
T25	1970	92	0	0
T26	2214	0	0	0
T27	2563	235	0	0
T28	1873	0	0	0
T29	2012	0	0	0
T30	2418	0	0	0
T33	0	30	0	0
T37	1411	0	0	0
T38	1772	64	0	0
T119	0	12	0	0
T120	0	125	0	0
T121	0	99	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91880284	89658425	0	2331
T5	5144	5123	0	3
T6	832	784	0	3
T7	1169	967	0	3
T8	1527	1371	0	3
T25	1970	1839	0	3
T26	2214	1758	0	3
T27	2563	2359	0	3
T28	1873	1807	0	3
T29	2012	1963	0	3
T30	2418	2340	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91880284	150272	0	0
T1	97408	92	0	0
T5	5144	0	0	0
T22	0	181	0	0
T23	0	114	0	0
T25	1970	60	0	0
T26	2214	365	0	0
T27	2563	80	0	0
T28	1873	0	0	0
T29	2012	0	0	0
T30	2418	0	0	0
T33	0	96	0	0
T37	1411	0	0	0
T38	1772	286	0	0
T120	0	101	0	0
T122	0	176	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91880284	89725433	0	0
T5	5144	5125	0	0
T6	832	786	0	0
T7	1169	969	0	0
T8	1527	1373	0	0
T25	1970	1849	0	0
T26	2214	1925	0	0
T27	2563	2370	0	0
T28	1873	1809	0	0
T29	2012	1965	0	0
T30	2418	2342	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91880284	87454	0	0
T1	97408	32	0	0
T5	5144	0	0	0
T22	0	73	0	0
T23	0	70	0	0
T25	1970	52	0	0
T26	2214	200	0	0
T27	2563	71	0	0
T28	1873	0	0	0
T29	2012	0	0	0
T30	2418	0	0	0
T33	0	53	0	0
T37	1411	0	0	0
T38	1772	96	0	0
T120	0	55	0	0
T122	0	48	0	0