Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1435873880	11418	0	0
TransStop_A	1435873880	6089	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1435873880	11418	0	0
T1	1391536	78	0	0
T2	800804	0	0	0
T18	5760	0	0	0
T19	38360	30	0	0
T20	9100	0	0	0
T28	29988	4	0	0
T29	17128	4	0	0
T30	19744	26	0	0
T37	5872	0	0	0
T38	28368	0	0	0
T80	0	41	0	0
T123	0	4	0	0
T124	0	3	0	0
T125	0	22	0	0
T126	0	4	0	0
T127	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1435873880	6089	0	0
T1	1391536	52	0	0
T2	800804	0	0	0
T18	5760	0	0	0
T19	38360	15	0	0
T20	9100	0	0	0
T28	29988	4	0	0
T29	17128	4	0	0
T30	19744	14	0	0
T37	5872	0	0	0
T38	28368	0	0	0
T80	0	20	0	0
T123	0	4	0	0
T124	0	3	0	0
T125	0	14	0	0
T126	0	4	0	0
T127	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	358968470	2807	0	0
TransStop_A	358968470	1459	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	358968470	2807	0	0
T1	347884	17	0	0
T2	200201	0	0	0
T18	1440	0	0	0
T19	9590	7	0	0
T20	2275	0	0	0
T28	7497	1	0	0
T29	4282	1	0	0
T30	4936	5	0	0
T37	1468	0	0	0
T38	7092	0	0	0
T80	0	10	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	0	4	0	0
T126	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	358968470	1459	0	0
T1	347884	9	0	0
T2	200201	0	0	0
T18	1440	0	0	0
T19	9590	4	0	0
T20	2275	0	0	0
T28	7497	1	0	0
T29	4282	1	0	0
T30	4936	2	0	0
T37	1468	0	0	0
T38	7092	0	0	0
T80	0	6	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	0	2	0	0
T126	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	358968470	2868	0	0
TransStop_A	358968470	1524	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	358968470	2868	0	0
T1	347884	20	0	0
T2	200201	0	0	0
T18	1440	0	0	0
T19	9590	9	0	0
T20	2275	0	0	0
T28	7497	1	0	0
T29	4282	1	0	0
T30	4936	3	0	0
T37	1468	0	0	0
T38	7092	0	0	0
T80	0	10	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	0	6	0	0
T126	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	358968470	1524	0	0
T1	347884	14	0	0
T2	200201	0	0	0
T18	1440	0	0	0
T19	9590	5	0	0
T20	2275	0	0	0
T28	7497	1	0	0
T29	4282	1	0	0
T30	4936	2	0	0
T37	1468	0	0	0
T38	7092	0	0	0
T80	0	5	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	0	4	0	0
T126	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	358968470	2872	0	0
TransStop_A	358968470	1536	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	358968470	2872	0	0
T1	347884	25	0	0
T2	200201	0	0	0
T18	1440	0	0	0
T19	9590	6	0	0
T20	2275	0	0	0
T28	7497	1	0	0
T29	4282	1	0	0
T30	4936	8	0	0
T37	1468	0	0	0
T38	7092	0	0	0
T80	0	13	0	0
T123	0	1	0	0
T125	0	9	0	0
T126	0	1	0	0
T127	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	358968470	1536	0	0
T1	347884	19	0	0
T2	200201	0	0	0
T18	1440	0	0	0
T19	9590	1	0	0
T20	2275	0	0	0
T28	7497	1	0	0
T29	4282	1	0	0
T30	4936	4	0	0
T37	1468	0	0	0
T38	7092	0	0	0
T80	0	7	0	0
T123	0	1	0	0
T125	0	6	0	0
T126	0	1	0	0
T127	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	358968470	2871	0	0
TransStop_A	358968470	1570	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	358968470	2871	0	0
T1	347884	16	0	0
T2	200201	0	0	0
T18	1440	0	0	0
T19	9590	8	0	0
T20	2275	0	0	0
T28	7497	1	0	0
T29	4282	1	0	0
T30	4936	10	0	0
T37	1468	0	0	0
T38	7092	0	0	0
T80	0	8	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	0	3	0	0
T126	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	358968470	1570	0	0
T1	347884	10	0	0
T2	200201	0	0	0
T18	1440	0	0	0
T19	9590	5	0	0
T20	2275	0	0	0
T28	7497	1	0	0
T29	4282	1	0	0
T30	4936	6	0	0
T37	1468	0	0	0
T38	7092	0	0	0
T80	0	2	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	0	2	0	0
T126	0	1	0	0