Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	91880284	11203348	0	58

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91880284	11203348	0	58
T1	97408	4049	0	0
T2	198199	48773	0	1
T3	0	24466	0	0
T4	83820	0	0	0
T11	0	7084	0	1
T12	0	12779	0	1
T13	0	112507	0	0
T14	0	23488	0	1
T15	0	6759	0	1
T16	0	70520	0	0
T17	0	126804	0	0
T18	1507	0	0	0
T19	2396	0	0	0
T20	1115	0	0	0
T21	1240	0	0	0
T22	1911	0	0	0
T23	1034	0	0	0
T24	916	0	0	0
T41	0	0	0	1
T91	0	0	0	1
T128	0	0	0	1
T129	0	0	0	1
T130	0	0	0	1