Assert Coverage for Module :
clkmgr_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
92815926 |
2354632 |
0 |
0 |
T17 |
312104 |
89996 |
0 |
0 |
T31 |
449453 |
158455 |
0 |
0 |
T32 |
333905 |
118930 |
0 |
0 |
T66 |
0 |
50622 |
0 |
0 |
T67 |
0 |
104864 |
0 |
0 |
T68 |
0 |
90969 |
0 |
0 |
T69 |
0 |
161430 |
0 |
0 |
T70 |
0 |
87296 |
0 |
0 |
T71 |
0 |
152055 |
0 |
0 |
T72 |
0 |
102869 |
0 |
0 |
T73 |
2412 |
0 |
0 |
0 |
T74 |
1489 |
0 |
0 |
0 |
T75 |
1469 |
0 |
0 |
0 |
T76 |
882 |
0 |
0 |
0 |
T77 |
112007 |
0 |
0 |
0 |
T78 |
1852 |
0 |
0 |
0 |
T79 |
25209 |
0 |
0 |
0 |
clk_enables_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
92815926 |
35487 |
0 |
0 |
T1 |
97408 |
0 |
0 |
0 |
T2 |
198199 |
0 |
0 |
0 |
T16 |
0 |
5 |
0 |
0 |
T17 |
0 |
3384 |
0 |
0 |
T18 |
1507 |
0 |
0 |
0 |
T19 |
2396 |
0 |
0 |
0 |
T20 |
1115 |
0 |
0 |
0 |
T28 |
1873 |
6 |
0 |
0 |
T29 |
2012 |
0 |
0 |
0 |
T30 |
2418 |
0 |
0 |
0 |
T37 |
1411 |
0 |
0 |
0 |
T38 |
1772 |
0 |
0 |
0 |
T66 |
0 |
1067 |
0 |
0 |
T69 |
0 |
6880 |
0 |
0 |
T77 |
0 |
3 |
0 |
0 |
T145 |
0 |
9 |
0 |
0 |
T146 |
0 |
3 |
0 |
0 |
T147 |
0 |
4 |
0 |
0 |
T148 |
0 |
2 |
0 |
0 |
clk_hints_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
92815926 |
30964 |
0 |
0 |
T1 |
97408 |
0 |
0 |
0 |
T2 |
198199 |
0 |
0 |
0 |
T16 |
0 |
7 |
0 |
0 |
T17 |
0 |
2734 |
0 |
0 |
T18 |
1507 |
0 |
0 |
0 |
T19 |
2396 |
0 |
0 |
0 |
T20 |
1115 |
0 |
0 |
0 |
T28 |
1873 |
2 |
0 |
0 |
T29 |
2012 |
5 |
0 |
0 |
T30 |
2418 |
0 |
0 |
0 |
T37 |
1411 |
0 |
0 |
0 |
T38 |
1772 |
0 |
0 |
0 |
T66 |
0 |
835 |
0 |
0 |
T69 |
0 |
6175 |
0 |
0 |
T77 |
0 |
4 |
0 |
0 |
T145 |
0 |
1 |
0 |
0 |
T146 |
0 |
1 |
0 |
0 |
T147 |
0 |
1 |
0 |
0 |
extclk_ctrl_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
92815926 |
40121 |
0 |
0 |
T1 |
97408 |
0 |
0 |
0 |
T2 |
198199 |
0 |
0 |
0 |
T16 |
0 |
144 |
0 |
0 |
T17 |
0 |
3693 |
0 |
0 |
T18 |
1507 |
0 |
0 |
0 |
T19 |
2396 |
0 |
0 |
0 |
T27 |
2563 |
62 |
0 |
0 |
T28 |
1873 |
0 |
0 |
0 |
T29 |
2012 |
0 |
0 |
0 |
T30 |
2418 |
0 |
0 |
0 |
T35 |
0 |
8 |
0 |
0 |
T37 |
1411 |
0 |
0 |
0 |
T38 |
1772 |
11 |
0 |
0 |
T81 |
0 |
25 |
0 |
0 |
T122 |
0 |
16 |
0 |
0 |
T149 |
0 |
44 |
0 |
0 |
T150 |
0 |
24 |
0 |
0 |
T151 |
0 |
8 |
0 |
0 |
extclk_ctrl_regwen_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
92815926 |
29606 |
0 |
0 |
T17 |
0 |
2880 |
0 |
0 |
T35 |
5023 |
6 |
0 |
0 |
T36 |
12935 |
0 |
0 |
0 |
T40 |
741 |
0 |
0 |
0 |
T43 |
0 |
5349 |
0 |
0 |
T66 |
0 |
1007 |
0 |
0 |
T69 |
0 |
5848 |
0 |
0 |
T81 |
0 |
11 |
0 |
0 |
T118 |
0 |
14 |
0 |
0 |
T122 |
1077 |
0 |
0 |
0 |
T123 |
974 |
0 |
0 |
0 |
T124 |
1257 |
0 |
0 |
0 |
T152 |
0 |
27 |
0 |
0 |
T153 |
0 |
3706 |
0 |
0 |
T154 |
0 |
2535 |
0 |
0 |
T155 |
888 |
0 |
0 |
0 |
T156 |
1323 |
0 |
0 |
0 |
T157 |
1203 |
0 |
0 |
0 |
T158 |
1695 |
0 |
0 |
0 |
jitter_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
92815926 |
42450 |
0 |
0 |
T1 |
97408 |
0 |
0 |
0 |
T2 |
198199 |
0 |
0 |
0 |
T16 |
0 |
204 |
0 |
0 |
T17 |
0 |
3860 |
0 |
0 |
T18 |
1507 |
0 |
0 |
0 |
T19 |
2396 |
0 |
0 |
0 |
T20 |
1115 |
0 |
0 |
0 |
T28 |
1873 |
121 |
0 |
0 |
T29 |
2012 |
73 |
0 |
0 |
T30 |
2418 |
0 |
0 |
0 |
T37 |
1411 |
0 |
0 |
0 |
T38 |
1772 |
0 |
0 |
0 |
T66 |
0 |
1629 |
0 |
0 |
T77 |
0 |
125 |
0 |
0 |
T126 |
0 |
67 |
0 |
0 |
T145 |
0 |
103 |
0 |
0 |
T146 |
0 |
96 |
0 |
0 |
T159 |
0 |
64 |
0 |
0 |
jitter_regwen_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
92815926 |
32308 |
0 |
0 |
T17 |
312104 |
3137 |
0 |
0 |
T31 |
449453 |
0 |
0 |
0 |
T32 |
333905 |
0 |
0 |
0 |
T43 |
0 |
6293 |
0 |
0 |
T58 |
0 |
27 |
0 |
0 |
T66 |
0 |
999 |
0 |
0 |
T69 |
0 |
6439 |
0 |
0 |
T73 |
2412 |
0 |
0 |
0 |
T74 |
1489 |
0 |
0 |
0 |
T75 |
1469 |
0 |
0 |
0 |
T76 |
882 |
0 |
0 |
0 |
T77 |
112007 |
0 |
0 |
0 |
T78 |
1852 |
0 |
0 |
0 |
T79 |
25209 |
0 |
0 |
0 |
T153 |
0 |
4121 |
0 |
0 |
T154 |
0 |
2509 |
0 |
0 |
T160 |
0 |
1705 |
0 |
0 |
T161 |
0 |
2880 |
0 |
0 |
T162 |
0 |
2608 |
0 |
0 |