Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	275640852	400	0	0
StatusRise_A	275640852	400	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	275640852	400	0	0
T5	15432	0	0	0
T8	4581	13	0	0
T18	0	9	0	0
T25	5910	0	0	0
T26	6642	0	0	0
T27	7689	0	0	0
T28	5619	0	0	0
T29	6036	0	0	0
T30	7254	0	0	0
T37	4233	5	0	0
T38	5316	0	0	0
T76	0	7	0	0
T155	0	1	0	0
T156	0	5	0	0
T158	0	15	0	0
T163	0	5	0	0
T164	0	5	0	0
T165	0	5	0	0
T166	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	275640852	400	0	0
T5	15432	0	0	0
T8	4581	13	0	0
T18	0	9	0	0
T25	5910	0	0	0
T26	6642	0	0	0
T27	7689	0	0	0
T28	5619	0	0	0
T29	6036	0	0	0
T30	7254	0	0	0
T37	4233	5	0	0
T38	5316	0	0	0
T76	0	7	0	0
T155	0	1	0	0
T156	0	5	0	0
T158	0	15	0	0
T163	0	5	0	0
T164	0	5	0	0
T165	0	5	0	0
T166	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	91880284	127	0	0
StatusRise_A	91880284	127	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91880284	127	0	0
T5	5144	0	0	0
T8	1527	4	0	0
T18	0	4	0	0
T25	1970	0	0	0
T26	2214	0	0	0
T27	2563	0	0	0
T28	1873	0	0	0
T29	2012	0	0	0
T30	2418	0	0	0
T37	1411	2	0	0
T38	1772	0	0	0
T76	0	1	0	0
T156	0	1	0	0
T158	0	5	0	0
T163	0	2	0	0
T164	0	1	0	0
T165	0	1	0	0
T166	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91880284	127	0	0
T5	5144	0	0	0
T8	1527	4	0	0
T18	0	4	0	0
T25	1970	0	0	0
T26	2214	0	0	0
T27	2563	0	0	0
T28	1873	0	0	0
T29	2012	0	0	0
T30	2418	0	0	0
T37	1411	2	0	0
T38	1772	0	0	0
T76	0	1	0	0
T156	0	1	0	0
T158	0	5	0	0
T163	0	2	0	0
T164	0	1	0	0
T165	0	1	0	0
T166	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	91880284	136	0	0
StatusRise_A	91880284	136	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91880284	136	0	0
T5	5144	0	0	0
T8	1527	5	0	0
T18	0	2	0	0
T25	1970	0	0	0
T26	2214	0	0	0
T27	2563	0	0	0
T28	1873	0	0	0
T29	2012	0	0	0
T30	2418	0	0	0
T37	1411	1	0	0
T38	1772	0	0	0
T76	0	3	0	0
T156	0	3	0	0
T158	0	6	0	0
T163	0	2	0	0
T164	0	2	0	0
T165	0	2	0	0
T166	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91880284	136	0	0
T5	5144	0	0	0
T8	1527	5	0	0
T18	0	2	0	0
T25	1970	0	0	0
T26	2214	0	0	0
T27	2563	0	0	0
T28	1873	0	0	0
T29	2012	0	0	0
T30	2418	0	0	0
T37	1411	1	0	0
T38	1772	0	0	0
T76	0	3	0	0
T156	0	3	0	0
T158	0	6	0	0
T163	0	2	0	0
T164	0	2	0	0
T165	0	2	0	0
T166	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	91880284	137	0	0
StatusRise_A	91880284	137	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91880284	137	0	0
T5	5144	0	0	0
T8	1527	4	0	0
T18	0	3	0	0
T25	1970	0	0	0
T26	2214	0	0	0
T27	2563	0	0	0
T28	1873	0	0	0
T29	2012	0	0	0
T30	2418	0	0	0
T37	1411	2	0	0
T38	1772	0	0	0
T76	0	3	0	0
T155	0	1	0	0
T156	0	1	0	0
T158	0	4	0	0
T163	0	1	0	0
T164	0	2	0	0
T165	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	91880284	137	0	0
T5	5144	0	0	0
T8	1527	4	0	0
T18	0	3	0	0
T25	1970	0	0	0
T26	2214	0	0	0
T27	2563	0	0	0
T28	1873	0	0	0
T29	2012	0	0	0
T30	2418	0	0	0
T37	1411	2	0	0
T38	1772	0	0	0
T76	0	3	0	0
T155	0	1	0	0
T156	0	1	0	0
T158	0	4	0	0
T163	0	1	0	0
T164	0	2	0	0
T165	0	2	0	0