Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T37,T1
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	34346	0	0
CgEnOn_A	2147483647	25969	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	34346	0	0
T1	0	17	0	0
T5	403684	3	0	0
T6	7107	3	0	0
T7	2617	6	0	0
T8	14880	47	0	0
T18	0	14	0	0
T19	0	7	0	0
T25	43754	3	0	0
T26	50582	3	0	0
T27	29118	3	0	0
T28	80754	7	0	0
T29	46140	7	0	0
T30	53222	8	0	0
T37	12602	7	0	0
T38	61731	0	0	0
T76	0	15	0	0
T156	0	16	0	0
T158	0	30	0	0
T163	0	10	0	0
T164	0	10	0	0
T165	0	10	0	0
T166	0	10	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	25969	0	0
T1	0	90	0	0
T5	403684	0	0	0
T7	2617	4	0	0
T8	14880	72	0	0
T18	0	46	0	0
T19	0	30	0	0
T20	0	18	0	0
T25	43754	0	0	0
T26	50582	0	0	0
T27	29118	0	0	0
T28	80754	8	0	0
T29	46140	8	0	0
T30	53222	26	0	0
T37	15732	24	0	0
T38	61731	0	0	0
T39	0	35	0	0
T76	0	20	0	0
T80	0	41	0	0
T155	0	2	0	0
T156	0	31	0	0
T158	0	44	0	0
T163	0	15	0	0
T164	0	14	0	0
T165	0	14	0	0
T166	0	12	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T37,T1
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	168061331	139	0	0
CgEnOn_A	168061331	139	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168061331	139	0	0
T5	17641	0	0	0
T8	596	5	0	0
T18	0	2	0	0
T25	2015	0	0	0
T26	2407	0	0	0
T27	1352	0	0	0
T28	3545	0	0	0
T29	2029	0	0	0
T30	2350	0	0	0
T37	669	1	0	0
T38	3590	0	0	0
T76	0	3	0	0
T156	0	3	0	0
T158	0	6	0	0
T163	0	2	0	0
T164	0	2	0	0
T165	0	2	0	0
T166	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168061331	139	0	0
T5	17641	0	0	0
T8	596	5	0	0
T18	0	2	0	0
T25	2015	0	0	0
T26	2407	0	0	0
T27	1352	0	0	0
T28	3545	0	0	0
T29	2029	0	0	0
T30	2350	0	0	0
T37	669	1	0	0
T38	3590	0	0	0
T76	0	3	0	0
T156	0	3	0	0
T158	0	6	0	0
T163	0	2	0	0
T164	0	2	0	0
T165	0	2	0	0
T166	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T37,T1
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	84030210	139	0	0
CgEnOn_A	84030210	139	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84030210	139	0	0
T5	8821	0	0	0
T8	298	5	0	0
T18	0	2	0	0
T25	1006	0	0	0
T26	1203	0	0	0
T27	676	0	0	0
T28	1773	0	0	0
T29	1015	0	0	0
T30	1175	0	0	0
T37	335	1	0	0
T38	1795	0	0	0
T76	0	3	0	0
T156	0	3	0	0
T158	0	6	0	0
T163	0	2	0	0
T164	0	2	0	0
T165	0	2	0	0
T166	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84030210	139	0	0
T5	8821	0	0	0
T8	298	5	0	0
T18	0	2	0	0
T25	1006	0	0	0
T26	1203	0	0	0
T27	676	0	0	0
T28	1773	0	0	0
T29	1015	0	0	0
T30	1175	0	0	0
T37	335	1	0	0
T38	1795	0	0	0
T76	0	3	0	0
T156	0	3	0	0
T158	0	6	0	0
T163	0	2	0	0
T164	0	2	0	0
T165	0	2	0	0
T166	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T37,T1
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	84030210	139	0	0
CgEnOn_A	84030210	139	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84030210	139	0	0
T5	8821	0	0	0
T8	298	5	0	0
T18	0	2	0	0
T25	1006	0	0	0
T26	1203	0	0	0
T27	676	0	0	0
T28	1773	0	0	0
T29	1015	0	0	0
T30	1175	0	0	0
T37	335	1	0	0
T38	1795	0	0	0
T76	0	3	0	0
T156	0	3	0	0
T158	0	6	0	0
T163	0	2	0	0
T164	0	2	0	0
T165	0	2	0	0
T166	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84030210	139	0	0
T5	8821	0	0	0
T8	298	5	0	0
T18	0	2	0	0
T25	1006	0	0	0
T26	1203	0	0	0
T27	676	0	0	0
T28	1773	0	0	0
T29	1015	0	0	0
T30	1175	0	0	0
T37	335	1	0	0
T38	1795	0	0	0
T76	0	3	0	0
T156	0	3	0	0
T158	0	6	0	0
T163	0	2	0	0
T164	0	2	0	0
T165	0	2	0	0
T166	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T37,T1
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	84030210	139	0	0
CgEnOn_A	84030210	139	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84030210	139	0	0
T5	8821	0	0	0
T8	298	5	0	0
T18	0	2	0	0
T25	1006	0	0	0
T26	1203	0	0	0
T27	676	0	0	0
T28	1773	0	0	0
T29	1015	0	0	0
T30	1175	0	0	0
T37	335	1	0	0
T38	1795	0	0	0
T76	0	3	0	0
T156	0	3	0	0
T158	0	6	0	0
T163	0	2	0	0
T164	0	2	0	0
T165	0	2	0	0
T166	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84030210	139	0	0
T5	8821	0	0	0
T8	298	5	0	0
T18	0	2	0	0
T25	1006	0	0	0
T26	1203	0	0	0
T27	676	0	0	0
T28	1773	0	0	0
T29	1015	0	0	0
T30	1175	0	0	0
T37	335	1	0	0
T38	1795	0	0	0
T76	0	3	0	0
T156	0	3	0	0
T158	0	6	0	0
T163	0	2	0	0
T164	0	2	0	0
T165	0	2	0	0
T166	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T37,T1
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	337456022	139	0	0
CgEnOn_A	337456022	137	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337456022	139	0	0
T5	35389	0	0	0
T8	1298	5	0	0
T18	0	2	0	0
T25	3860	0	0	0
T26	4428	0	0	0
T27	2563	0	0	0
T28	7197	0	0	0
T29	4110	0	0	0
T30	4737	0	0	0
T37	1445	1	0	0
T38	6807	0	0	0
T76	0	3	0	0
T156	0	3	0	0
T158	0	6	0	0
T163	0	2	0	0
T164	0	2	0	0
T165	0	2	0	0
T166	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337456022	137	0	0
T5	35389	0	0	0
T8	1298	5	0	0
T18	0	2	0	0
T25	3860	0	0	0
T26	4428	0	0	0
T27	2563	0	0	0
T28	7197	0	0	0
T29	4110	0	0	0
T30	4737	0	0	0
T37	1445	1	0	0
T38	6807	0	0	0
T76	0	3	0	0
T156	0	3	0	0
T158	0	6	0	0
T163	0	2	0	0
T164	0	2	0	0
T165	0	2	0	0
T166	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T37,T1
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	358968050	127	0	0
CgEnOn_A	358968050	127	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	358968050	127	0	0
T5	36865	0	0	0
T8	1419	4	0	0
T18	0	4	0	0
T25	4020	0	0	0
T26	4612	0	0	0
T27	2670	0	0	0
T28	7497	0	0	0
T29	4282	0	0	0
T30	4935	0	0	0
T37	1467	2	0	0
T38	7091	0	0	0
T76	0	1	0	0
T156	0	1	0	0
T158	0	5	0	0
T163	0	2	0	0
T164	0	1	0	0
T165	0	1	0	0
T166	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	358968050	127	0	0
T5	36865	0	0	0
T8	1419	4	0	0
T18	0	4	0	0
T25	4020	0	0	0
T26	4612	0	0	0
T27	2670	0	0	0
T28	7497	0	0	0
T29	4282	0	0	0
T30	4935	0	0	0
T37	1467	2	0	0
T38	7091	0	0	0
T76	0	1	0	0
T156	0	1	0	0
T158	0	5	0	0
T163	0	2	0	0
T164	0	1	0	0
T165	0	1	0	0
T166	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T37,T1
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	358968050	127	0	0
CgEnOn_A	358968050	127	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	358968050	127	0	0
T5	36865	0	0	0
T8	1419	4	0	0
T18	0	4	0	0
T25	4020	0	0	0
T26	4612	0	0	0
T27	2670	0	0	0
T28	7497	0	0	0
T29	4282	0	0	0
T30	4935	0	0	0
T37	1467	2	0	0
T38	7091	0	0	0
T76	0	1	0	0
T156	0	1	0	0
T158	0	5	0	0
T163	0	2	0	0
T164	0	1	0	0
T165	0	1	0	0
T166	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	358968050	127	0	0
T5	36865	0	0	0
T8	1419	4	0	0
T18	0	4	0	0
T25	4020	0	0	0
T26	4612	0	0	0
T27	2670	0	0	0
T28	7497	0	0	0
T29	4282	0	0	0
T30	4935	0	0	0
T37	1467	2	0	0
T38	7091	0	0	0
T76	0	1	0	0
T156	0	1	0	0
T158	0	5	0	0
T163	0	2	0	0
T164	0	1	0	0
T165	0	1	0	0
T166	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T37,T1
1	0	Unreachable
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	172257682	139	0	0
CgEnOn_A	172257682	137	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172257682	139	0	0
T5	20575	0	0	0
T8	693	4	0	0
T18	0	3	0	0
T25	1930	0	0	0
T26	2214	0	0	0
T27	1282	0	0	0
T28	3598	0	0	0
T29	2055	0	0	0
T30	2369	0	0	0
T37	681	2	0	0
T38	3403	0	0	0
T76	0	3	0	0
T155	0	1	0	0
T156	0	1	0	0
T158	0	4	0	0
T163	0	1	0	0
T164	0	2	0	0
T165	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172257682	137	0	0
T5	20575	0	0	0
T8	693	4	0	0
T18	0	3	0	0
T25	1930	0	0	0
T26	2214	0	0	0
T27	1282	0	0	0
T28	3598	0	0	0
T29	2055	0	0	0
T30	2369	0	0	0
T37	681	2	0	0
T38	3403	0	0	0
T76	0	3	0	0
T155	0	1	0	0
T156	0	1	0	0
T158	0	4	0	0
T163	0	1	0	0
T164	0	2	0	0
T165	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T37,T18
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	84030210	5313	0	0
CgEnOn_A	84030210	3221	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84030210	5313	0	0
T5	8821	1	0	0
T6	770	1	0	0
T7	275	2	0	0
T8	298	6	0	0
T25	1006	1	0	0
T26	1203	1	0	0
T27	676	1	0	0
T28	1773	2	0	0
T29	1015	2	0	0
T30	1175	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84030210	3221	0	0
T1	0	3	0	0
T5	8821	0	0	0
T7	275	1	0	0
T8	298	5	0	0
T18	0	2	0	0
T20	0	4	0	0
T25	1006	0	0	0
T26	1203	0	0	0
T27	676	0	0	0
T28	1773	1	0	0
T29	1015	1	0	0
T30	1175	0	0	0
T37	335	1	0	0
T39	0	9	0	0
T156	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T37,T18
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	168061331	5337	0	0
CgEnOn_A	168061331	3245	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168061331	5337	0	0
T5	17641	1	0	0
T6	1539	1	0	0
T7	551	2	0	0
T8	596	6	0	0
T25	2015	1	0	0
T26	2407	1	0	0
T27	1352	1	0	0
T28	3545	2	0	0
T29	2029	2	0	0
T30	2350	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168061331	3245	0	0
T1	0	3	0	0
T5	17641	0	0	0
T7	551	1	0	0
T8	596	5	0	0
T18	0	2	0	0
T20	0	5	0	0
T25	2015	0	0	0
T26	2407	0	0	0
T27	1352	0	0	0
T28	3545	1	0	0
T29	2029	1	0	0
T30	2350	0	0	0
T37	669	1	0	0
T39	0	8	0	0
T156	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T37,T18
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	337456022	5358	0	0
CgEnOn_A	337456022	3264	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337456022	5358	0	0
T5	35389	1	0	0
T6	3199	1	0	0
T7	1194	2	0	0
T8	1298	6	0	0
T25	3860	1	0	0
T26	4428	1	0	0
T27	2563	1	0	0
T28	7197	2	0	0
T29	4110	2	0	0
T30	4737	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337456022	3264	0	0
T1	0	3	0	0
T5	35389	0	0	0
T7	1194	1	0	0
T8	1298	5	0	0
T18	0	2	0	0
T20	0	4	0	0
T25	3860	0	0	0
T26	4428	0	0	0
T27	2563	0	0	0
T28	7197	1	0	0
T29	4110	1	0	0
T30	4737	0	0	0
T37	1445	1	0	0
T39	0	8	0	0
T156	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T37,T18
1	0	Covered	T6,T7,T8
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	172257682	5324	0	0
CgEnOn_A	172257682	3229	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172257682	5324	0	0
T5	20575	1	0	0
T6	1599	1	0	0
T7	597	2	0	0
T8	693	5	0	0
T25	1930	1	0	0
T26	2214	1	0	0
T27	1282	1	0	0
T28	3598	2	0	0
T29	2055	2	0	0
T30	2369	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172257682	3229	0	0
T1	0	3	0	0
T5	20575	0	0	0
T7	597	1	0	0
T8	693	4	0	0
T18	0	3	0	0
T20	0	5	0	0
T25	1930	0	0	0
T26	2214	0	0	0
T27	1282	0	0	0
T28	3598	1	0	0
T29	2055	1	0	0
T30	2369	0	0	0
T37	681	2	0	0
T39	0	10	0	0
T155	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T37,T1
1	0	Covered	T28,T29,T30
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	358968050	2934	0	0
CgEnOn_A	358968050	2934	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	358968050	2934	0	0
T1	0	17	0	0
T5	36865	0	0	0
T8	1419	4	0	0
T18	0	4	0	0
T19	0	7	0	0
T25	4020	0	0	0
T26	4612	0	0	0
T27	2670	0	0	0
T28	7497	1	0	0
T29	4282	1	0	0
T30	4935	5	0	0
T37	1467	2	0	0
T38	7091	0	0	0
T80	0	10	0	0
T156	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	358968050	2934	0	0
T1	0	17	0	0
T5	36865	0	0	0
T8	1419	4	0	0
T18	0	4	0	0
T19	0	7	0	0
T25	4020	0	0	0
T26	4612	0	0	0
T27	2670	0	0	0
T28	7497	1	0	0
T29	4282	1	0	0
T30	4935	5	0	0
T37	1467	2	0	0
T38	7091	0	0	0
T80	0	10	0	0
T156	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T37,T1
1	0	Covered	T28,T29,T30
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	358968050	2995	0	0
CgEnOn_A	358968050	2995	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	358968050	2995	0	0
T1	0	20	0	0
T5	36865	0	0	0
T8	1419	4	0	0
T18	0	4	0	0
T19	0	9	0	0
T25	4020	0	0	0
T26	4612	0	0	0
T27	2670	0	0	0
T28	7497	1	0	0
T29	4282	1	0	0
T30	4935	3	0	0
T37	1467	2	0	0
T38	7091	0	0	0
T80	0	10	0	0
T156	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	358968050	2995	0	0
T1	0	20	0	0
T5	36865	0	0	0
T8	1419	4	0	0
T18	0	4	0	0
T19	0	9	0	0
T25	4020	0	0	0
T26	4612	0	0	0
T27	2670	0	0	0
T28	7497	1	0	0
T29	4282	1	0	0
T30	4935	3	0	0
T37	1467	2	0	0
T38	7091	0	0	0
T80	0	10	0	0
T156	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T37,T1
1	0	Covered	T28,T29,T30
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	358968050	2999	0	0
CgEnOn_A	358968050	2999	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	358968050	2999	0	0
T1	0	25	0	0
T5	36865	0	0	0
T8	1419	4	0	0
T18	0	4	0	0
T19	0	6	0	0
T25	4020	0	0	0
T26	4612	0	0	0
T27	2670	0	0	0
T28	7497	1	0	0
T29	4282	1	0	0
T30	4935	8	0	0
T37	1467	2	0	0
T38	7091	0	0	0
T80	0	13	0	0
T156	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	358968050	2999	0	0
T1	0	25	0	0
T5	36865	0	0	0
T8	1419	4	0	0
T18	0	4	0	0
T19	0	6	0	0
T25	4020	0	0	0
T26	4612	0	0	0
T27	2670	0	0	0
T28	7497	1	0	0
T29	4282	1	0	0
T30	4935	8	0	0
T37	1467	2	0	0
T38	7091	0	0	0
T80	0	13	0	0
T156	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T8,T37,T1
1	0	Covered	T28,T29,T30
1	1	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	358968050	2998	0	0
CgEnOn_A	358968050	2998	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	358968050	2998	0	0
T1	0	16	0	0
T5	36865	0	0	0
T8	1419	4	0	0
T18	0	4	0	0
T19	0	8	0	0
T25	4020	0	0	0
T26	4612	0	0	0
T27	2670	0	0	0
T28	7497	1	0	0
T29	4282	1	0	0
T30	4935	10	0	0
T37	1467	2	0	0
T38	7091	0	0	0
T80	0	8	0	0
T156	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	358968050	2998	0	0
T1	0	16	0	0
T5	36865	0	0	0
T8	1419	4	0	0
T18	0	4	0	0
T19	0	8	0	0
T25	4020	0	0	0
T26	4612	0	0	0
T27	2670	0	0	0
T28	7497	1	0	0
T29	4282	1	0	0
T30	4935	10	0	0
T37	1467	2	0	0
T38	7091	0	0	0
T80	0	8	0	0
T156	0	1	0	0