Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	281090	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1259278

1

T5

45

T4

329

T23

11

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	398516	1			T5	60		T6	100		T4	336
values[0x0]	527778	1			T5	27		T4	168		T23	13
values[0x1]	614074	1			T5	18		T4	154		T23	14

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	169342	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1371026

1

T5

51

T6

40

T4

419

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6882	1			T1	537		T19	1		T30	10
valid_sources[0x01]	6205	1			T6	1		T1	450		T3	1
valid_sources[0x02]	5922	1			T1	173		T2	2		T19	1
valid_sources[0x03]	6087	1			T5	1		T4	1		T1	304
valid_sources[0x04]	5548	1			T1	187		T2	2		T20	5
valid_sources[0x05]	5910	1			T1	250		T2	7		T30	8
valid_sources[0x06]	6187	1			T5	1		T25	21		T1	751
valid_sources[0x07]	5343	1			T4	4		T1	226		T2	4
valid_sources[0x08]	6924	1			T5	1		T4	6		T1	697
valid_sources[0x09]	5522	1			T1	155		T20	2		T30	4
valid_sources[0x0a]	5672	1			T1	129		T30	2		T9	3
valid_sources[0x0b]	6016	1			T4	2		T1	198		T20	2
valid_sources[0x0c]	5324	1			T4	5		T1	29		T2	5
valid_sources[0x0d]	5710	1			T5	1		T1	506		T19	1
valid_sources[0x0e]	5512	1			T4	2		T1	184		T3	2
valid_sources[0x0f]	6872	1			T5	1		T4	4		T1	39
valid_sources[0x10]	8625	1			T1	314		T30	4		T9	4
valid_sources[0x11]	5847	1			T6	1		T4	11		T1	255
valid_sources[0x12]	5366	1			T1	314		T20	1		T30	1
valid_sources[0x13]	7095	1			T6	1		T4	11		T1	88
valid_sources[0x14]	6046	1			T1	256		T20	9		T30	1
valid_sources[0x15]	5434	1			T1	136		T3	1		T19	1
valid_sources[0x16]	6849	1			T4	8		T1	10		T3	2
valid_sources[0x17]	6260	1			T5	1		T6	1		T1	169
valid_sources[0x18]	5777	1			T1	45		T20	1		T30	3
valid_sources[0x19]	5455	1			T1	84		T3	2		T20	1
valid_sources[0x1a]	5826	1			T1	386		T20	1		T30	1
valid_sources[0x1b]	6234	1			T4	18		T1	478		T2	3
valid_sources[0x1c]	6040	1			T4	3		T1	96		T2	9
valid_sources[0x1d]	5571	1			T1	115		T3	3		T20	2
valid_sources[0x1e]	5529	1			T5	1		T4	2		T1	26
valid_sources[0x1f]	5950	1			T5	1		T6	1		T4	3
valid_sources[0x20]	5327	1			T6	1		T1	51		T2	12
valid_sources[0x21]	5827	1			T6	1		T1	244		T2	11
valid_sources[0x22]	5685	1			T6	3		T4	12		T1	184
valid_sources[0x23]	7508	1			T1	134		T2	3		T30	2
valid_sources[0x24]	6198	1			T4	8		T1	209		T20	9
valid_sources[0x25]	6365	1			T1	534		T2	9		T30	3
valid_sources[0x26]	6230	1			T5	1		T1	211		T2	1
valid_sources[0x27]	6056	1			T4	1		T1	89		T2	3
valid_sources[0x28]	6829	1			T5	1		T6	2		T1	335
valid_sources[0x29]	7717	1			T5	1		T1	147		T19	1
valid_sources[0x2a]	5909	1			T1	281		T2	2		T20	4
valid_sources[0x2b]	6335	1			T1	155		T2	1		T3	1
valid_sources[0x2c]	5624	1			T6	1		T1	324		T2	10
valid_sources[0x2d]	5680	1			T4	4		T23	1		T1	201
valid_sources[0x2e]	5996	1			T6	1		T1	280		T3	1
valid_sources[0x2f]	6223	1			T5	3		T1	325		T20	3
valid_sources[0x30]	6146	1			T4	1		T23	8		T1	23
valid_sources[0x31]	6100	1			T5	2		T4	2		T1	281
valid_sources[0x32]	6467	1			T5	3		T4	1		T1	822
valid_sources[0x33]	6761	1			T1	29		T30	3		T9	9
valid_sources[0x34]	5834	1			T6	3		T4	12		T1	240
valid_sources[0x35]	5245	1			T5	1		T6	1		T4	11
valid_sources[0x36]	5313	1			T5	1		T1	235		T2	4
valid_sources[0x37]	6050	1			T1	135		T2	5		T20	2
valid_sources[0x38]	6229	1			T4	2		T1	87		T2	5
valid_sources[0x39]	6046	1			T4	5		T1	293		T30	4
valid_sources[0x3a]	6006	1			T4	5		T1	111		T2	1
valid_sources[0x3b]	6084	1			T5	1		T4	1		T1	321
valid_sources[0x3c]	5400	1			T6	2		T4	15		T1	134
valid_sources[0x3d]	5587	1			T6	1		T1	270		T30	6
valid_sources[0x3e]	6441	1			T6	2		T1	881		T3	1
valid_sources[0x3f]	6058	1			T6	1		T4	8		T1	209
valid_sources[0x40]	6097	1			T4	4		T1	282		T20	4
valid_sources[0x41]	6018	1			T1	12		T2	1		T3	6
valid_sources[0x42]	5625	1			T5	1		T1	136		T2	6
valid_sources[0x43]	5967	1			T5	1		T6	2		T1	231
valid_sources[0x44]	8272	1			T5	1		T6	1		T1	485
valid_sources[0x45]	5366	1			T4	1		T1	403		T2	18
valid_sources[0x46]	6430	1			T4	3		T1	694		T3	1
valid_sources[0x47]	5187	1			T23	4		T1	40		T2	6
valid_sources[0x48]	6195	1			T5	1		T6	1		T4	7
valid_sources[0x49]	5512	1			T5	1		T1	135		T3	1
valid_sources[0x4a]	6670	1			T5	1		T6	1		T1	18
valid_sources[0x4b]	6254	1			T23	1		T1	443		T3	1
valid_sources[0x4c]	5807	1			T4	3		T1	168		T3	3
valid_sources[0x4d]	5449	1			T6	1		T1	197		T2	20
valid_sources[0x4e]	5883	1			T5	1		T1	124		T3	3
valid_sources[0x4f]	6386	1			T4	1		T1	55		T2	28
valid_sources[0x50]	5434	1			T1	107		T2	1		T3	1
valid_sources[0x51]	6766	1			T4	8		T1	61		T2	3
valid_sources[0x52]	5350	1			T1	169		T2	3		T3	1
valid_sources[0x53]	5639	1			T6	1		T4	4		T1	276
valid_sources[0x54]	6363	1			T1	290		T2	2		T3	2
valid_sources[0x55]	5862	1			T4	4		T1	216		T2	5
valid_sources[0x56]	5939	1			T6	1		T1	41		T3	3
valid_sources[0x57]	5234	1			T5	1		T6	2		T1	88
valid_sources[0x58]	5752	1			T4	11		T1	385		T2	4
valid_sources[0x59]	5557	1			T5	2		T1	183		T2	9
valid_sources[0x5a]	5129	1			T1	95		T30	3		T9	7
valid_sources[0x5b]	5814	1			T5	2		T1	152		T20	1
valid_sources[0x5c]	5909	1			T6	2		T4	11		T23	2
valid_sources[0x5d]	6496	1			T4	2		T1	15		T2	5
valid_sources[0x5e]	6183	1			T6	1		T4	7		T1	355
valid_sources[0x5f]	6051	1			T4	4		T1	609		T2	8
valid_sources[0x60]	6342	1			T4	8		T1	178		T17	12
valid_sources[0x61]	5774	1			T6	1		T1	232		T2	3
valid_sources[0x62]	6037	1			T1	199		T3	1		T19	1
valid_sources[0x63]	5875	1			T4	2		T1	283		T3	1
valid_sources[0x64]	5712	1			T5	3		T1	312		T20	5
valid_sources[0x65]	5400	1			T4	10		T1	125		T2	8
valid_sources[0x66]	5843	1			T4	4		T1	296		T2	1
valid_sources[0x67]	6205	1			T5	2		T4	1		T1	240
valid_sources[0x68]	5179	1			T4	4		T1	116		T2	2
valid_sources[0x69]	6016	1			T1	619		T2	13		T20	1
valid_sources[0x6a]	7020	1			T6	3		T1	550		T30	2
valid_sources[0x6b]	5825	1			T5	1		T4	2		T1	42
valid_sources[0x6c]	6135	1			T1	261		T2	1		T20	1
valid_sources[0x6d]	5620	1			T1	37		T17	12		T3	1
valid_sources[0x6e]	5945	1			T5	1		T6	1		T4	2
valid_sources[0x6f]	5589	1			T1	114		T2	2		T19	1
valid_sources[0x70]	6004	1			T6	1		T1	61		T3	1
valid_sources[0x71]	5319	1			T1	32		T2	4		T3	1
valid_sources[0x72]	5966	1			T1	28		T20	1		T30	2
valid_sources[0x73]	5707	1			T1	118		T2	18		T19	1
valid_sources[0x74]	5880	1			T6	1		T4	3		T1	248
valid_sources[0x75]	5766	1			T6	2		T4	1		T1	143
valid_sources[0x76]	8888	1			T1	270		T20	1		T30	5
valid_sources[0x77]	5684	1			T5	1		T1	194		T2	3
valid_sources[0x78]	6118	1			T5	1		T4	9		T1	36
valid_sources[0x79]	5906	1			T1	20		T3	1		T19	1
valid_sources[0x7a]	5776	1			T4	18		T1	117		T20	1
valid_sources[0x7b]	6154	1			T5	1		T4	10		T1	536
valid_sources[0x7c]	5592	1			T5	1		T6	1		T1	200
valid_sources[0x7d]	6315	1			T5	2		T6	1		T4	3
valid_sources[0x7e]	6931	1			T5	1		T6	1		T4	5
valid_sources[0x7f]	5626	1			T1	352		T2	5		T30	3
valid_sources[0x80]	5404	1			T1	34		T20	2		T30	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

325440

1

T5

36

T4

170

T23

7

values[0x0]

all_enables

biggest_size

479178

1

T5

7

T4

103

T23

2

values[0x1]

all_enables

biggest_size

454660

1

T5

2

T4

56

T23

2