Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T1
0	1	Covered	T1,T16,T2
1	0	Covered	T5,T6,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T1
1	0	Covered	T36,T37,T38
1	1	Covered	T5,T6,T4

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	441138812	7342	0	0
GateOpen_A	441138812	13902	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441138812	7342	0	0
T1	1644164	125	0	0
T2	667217	4	0	0
T3	120051	0	0	0
T9	0	4	0	0
T10	0	98	0	0
T11	0	144	0	0
T13	0	10	0	0
T16	3228	8	0	0
T17	5522	0	0	0
T18	7998	0	0	0
T19	22630	0	0	0
T20	203268	0	0	0
T21	8865	11	0	0
T22	10022	0	0	0
T36	0	13	0	0
T37	0	8	0	0
T137	0	3	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441138812	13902	0	0
T1	1644164	145	0	0
T2	667217	8	0	0
T3	0	4	0	0
T4	176310	60	0	0
T6	74241	404	0	0
T16	3228	12	0	0
T17	5522	4	0	0
T18	7998	4	0	0
T23	4938	0	0	0
T24	3222	4	0	0
T25	3673	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T1
0	1	Covered	T1,T16,T2
1	0	Covered	T5,T6,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T1
1	0	Covered	T36,T37,T38
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	48462123	1746	0	0
GateOpen_A	48462123	3386	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48462123	1746	0	0
T1	913016	27	0	0
T2	72469	1	0	0
T3	13330	0	0	0
T9	0	1	0	0
T10	0	23	0	0
T11	0	38	0	0
T13	0	10	0	0
T16	350	1	0	0
T17	631	0	0	0
T18	883	0	0	0
T19	2702	0	0	0
T20	16744	0	0	0
T21	965	3	0	0
T22	1139	0	0	0
T36	0	3	0	0
T37	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48462123	3386	0	0
T1	913016	32	0	0
T2	72469	2	0	0
T3	0	1	0	0
T4	12777	15	0	0
T6	6935	101	0	0
T16	350	2	0	0
T17	631	1	0	0
T18	883	1	0	0
T23	558	0	0	0
T24	336	1	0	0
T25	402	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T1
0	1	Covered	T1,T16,T2
1	0	Covered	T5,T6,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T1
1	0	Covered	T36,T37,T38
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	96924571	1865	0	0
GateOpen_A	96924571	3505	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96924571	1865	0	0
T1	182603	38	0	0
T2	144939	1	0	0
T3	26660	0	0	0
T9	0	1	0	0
T10	0	25	0	0
T11	0	33	0	0
T16	700	3	0	0
T17	1265	0	0	0
T18	1765	0	0	0
T19	5405	0	0	0
T20	33484	0	0	0
T21	1930	2	0	0
T22	2278	0	0	0
T36	0	3	0	0
T37	0	2	0	0
T137	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96924571	3505	0	0
T1	182603	43	0	0
T2	144939	2	0	0
T3	0	1	0	0
T4	25550	15	0	0
T6	13872	101	0	0
T16	700	4	0	0
T17	1265	1	0	0
T18	1765	1	0	0
T23	1118	0	0	0
T24	671	1	0	0
T25	804	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T1
0	1	Covered	T1,T16,T2
1	0	Covered	T5,T6,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T1
1	0	Covered	T36,T37,T38
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	195408662	1864	0	0
GateOpen_A	195408662	3504	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195408662	1864	0	0
T1	365307	31	0	0
T2	290268	1	0	0
T3	53373	0	0	0
T9	0	1	0	0
T10	0	25	0	0
T11	0	37	0	0
T16	1452	2	0	0
T17	2417	0	0	0
T18	3567	0	0	0
T19	9682	0	0	0
T20	102025	0	0	0
T21	3980	3	0	0
T22	4403	0	0	0
T36	0	3	0	0
T37	0	2	0	0
T137	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195408662	3504	0	0
T1	365307	36	0	0
T2	290268	2	0	0
T3	0	1	0	0
T4	91987	15	0	0
T6	35622	101	0	0
T16	1452	3	0	0
T17	2417	1	0	0
T18	3567	1	0	0
T23	2175	0	0	0
T24	1477	1	0	0
T25	1645	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T1
0	1	Covered	T1,T16,T2
1	0	Covered	T5,T6,T4

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T1
1	0	Covered	T36,T37,T38
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	100343456	1867	0	0
GateOpen_A	100343456	3507	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100343456	1867	0	0
T1	183238	29	0	0
T2	159541	1	0	0
T3	26688	0	0	0
T9	0	1	0	0
T10	0	25	0	0
T11	0	36	0	0
T16	726	2	0	0
T17	1209	0	0	0
T18	1783	0	0	0
T19	4841	0	0	0
T20	51015	0	0	0
T21	1990	3	0	0
T22	2202	0	0	0
T36	0	4	0	0
T37	0	2	0	0
T137	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100343456	3507	0	0
T1	183238	34	0	0
T2	159541	2	0	0
T3	0	1	0	0
T4	45996	15	0	0
T6	17812	101	0	0
T16	726	3	0	0
T17	1209	1	0	0
T18	1783	1	0	0
T23	1087	0	0	0
T24	738	1	0	0
T25	822	1	0	0