Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	343628100	37418	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	343628100	37418	0	0
T1	850400	797	0	0
T2	860930	77	0	0
T3	266860	182	0	0
T9	0	154	0	0
T10	0	326	0	0
T11	0	623	0	0
T12	0	135	0	0
T13	0	320	0	0
T14	0	151	0	0
T15	0	56	0	0
T16	7335	0	0	0
T17	12465	0	0	0
T18	12450	0	0	0
T19	7560	0	0	0
T20	132845	0	0	0
T21	5180	0	0	0
T22	5500	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	68725620	5490	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68725620	5490	0	0
T1	170080	119	0	0
T2	172186	11	0	0
T3	53372	27	0	0
T9	0	30	0	0
T10	0	49	0	0
T11	0	106	0	0
T12	0	19	0	0
T13	0	44	0	0
T14	0	22	0	0
T15	0	9	0	0
T16	1467	0	0	0
T17	2493	0	0	0
T18	2490	0	0	0
T19	1512	0	0	0
T20	26569	0	0	0
T21	1036	0	0	0
T22	1100	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	68725620	5433	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68725620	5433	0	0
T1	170080	116	0	0
T2	172186	11	0	0
T3	53372	22	0	0
T9	0	30	0	0
T10	0	41	0	0
T11	0	106	0	0
T12	0	19	0	0
T13	0	42	0	0
T14	0	22	0	0
T15	0	9	0	0
T16	1467	0	0	0
T17	2493	0	0	0
T18	2490	0	0	0
T19	1512	0	0	0
T20	26569	0	0	0
T21	1036	0	0	0
T22	1100	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	68725620	7519	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68725620	7519	0	0
T1	170080	161	0	0
T2	172186	15	0	0
T3	53372	35	0	0
T9	0	30	0	0
T10	0	64	0	0
T11	0	127	0	0
T12	0	30	0	0
T13	0	65	0	0
T14	0	30	0	0
T15	0	11	0	0
T16	1467	0	0	0
T17	2493	0	0	0
T18	2490	0	0	0
T19	1512	0	0	0
T20	26569	0	0	0
T21	1036	0	0	0
T22	1100	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	68725620	7496	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68725620	7496	0	0
T1	170080	160	0	0
T2	172186	16	0	0
T3	53372	39	0	0
T9	0	30	0	0
T10	0	65	0	0
T11	0	126	0	0
T12	0	26	0	0
T13	0	65	0	0
T14	0	30	0	0
T15	0	12	0	0
T16	1467	0	0	0
T17	2493	0	0	0
T18	2490	0	0	0
T19	1512	0	0	0
T20	26569	0	0	0
T21	1036	0	0	0
T22	1100	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	68725620	11480	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68725620	11480	0	0
T1	170080	241	0	0
T2	172186	24	0	0
T3	53372	59	0	0
T9	0	34	0	0
T10	0	107	0	0
T11	0	158	0	0
T12	0	41	0	0
T13	0	104	0	0
T14	0	47	0	0
T15	0	15	0	0
T16	1467	0	0	0
T17	2493	0	0	0
T18	2490	0	0	0
T19	1512	0	0	0
T20	26569	0	0	0
T21	1036	0	0	0
T22	1100	0	0	0