Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T4
0	1	Unreachable
1	0	Covered	T6,T4,T1

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	68725620	66442627	0	0
AllClkBypReqTrue_A	68725620	69657	0	0
IoClkBypReqFalse_A	68725620	66393162	0	2325
IoClkBypReqTrue_A	68725620	114668	0	0
LcClkBypAckFalse_A	68725620	66446763	0	0
LcClkBypAckTrue_A	68725620	65521	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68725620	66442627	0	0
T1	170080	169751	0	0
T4	45996	6047	0	0
T5	2552	2353	0	0
T6	18553	10000	0	0
T16	1467	1357	0	0
T17	2493	2353	0	0
T18	2490	2385	0	0
T23	2197	1954	0	0
T24	1507	1313	0	0
T25	1696	1585	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68725620	69657	0	0
T1	170080	580	0	0
T2	172186	0	0	0
T3	53372	0	0	0
T9	0	124	0	0
T10	0	541	0	0
T16	1467	0	0	0
T17	2493	0	0	0
T18	2490	0	0	0
T19	1512	113	0	0
T22	0	53	0	0
T23	2197	78	0	0
T24	1507	0	0	0
T25	1696	0	0	0
T98	0	33	0	0
T99	0	34	0	0
T100	0	77	0	0
T101	0	125	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68725620	66393162	0	2325
T1	170080	169704	0	3
T4	45996	6017	0	3
T5	2552	2351	0	3
T6	18553	9798	0	3
T16	1467	1355	0	3
T17	2493	1963	0	3
T18	2490	2383	0	3
T23	2197	1998	0	3
T24	1507	1311	0	3
T25	1696	1583	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68725620	114668	0	0
T1	170080	1034	0	0
T2	172186	0	0	0
T3	53372	0	0	0
T9	0	529	0	0
T10	0	1342	0	0
T16	1467	0	0	0
T17	2493	388	0	0
T18	2490	0	0	0
T19	1512	252	0	0
T22	0	31	0	0
T23	2197	32	0	0
T24	1507	0	0	0
T25	1696	0	0	0
T98	0	32	0	0
T100	0	316	0	0
T101	0	105	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68725620	66446763	0	0
T1	170080	169748	0	0
T4	45996	6047	0	0
T5	2552	2353	0	0
T6	18553	10000	0	0
T16	1467	1357	0	0
T17	2493	2205	0	0
T18	2490	2385	0	0
T23	2197	2004	0	0
T24	1507	1313	0	0
T25	1696	1585	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68725620	65521	0	0
T1	170080	610	0	0
T2	172186	0	0	0
T3	53372	0	0	0
T9	0	260	0	0
T10	0	655	0	0
T16	1467	0	0	0
T17	2493	148	0	0
T18	2490	0	0	0
T19	1512	165	0	0
T22	0	26	0	0
T23	2197	28	0	0
T24	1507	0	0	0
T25	1696	0	0	0
T98	0	15	0	0
T100	0	213	0	0
T101	0	72	0	0