Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	836305424	8698	0	0
TransStop_A	836305424	4571	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	836305424	8698	0	0
T1	1538960	83	0	0
T2	0	8	0	0
T4	383296	0	0	0
T5	10212	30	0	0
T6	148428	0	0	0
T9	0	27	0	0
T10	0	240	0	0
T11	0	195	0	0
T13	0	29	0	0
T15	0	160	0	0
T16	6048	0	0	0
T17	10068	0	0	0
T18	14860	35	0	0
T23	9060	0	0	0
T24	6152	0	0	0
T25	6852	0	0	0
T26	0	46	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	836305424	4571	0	0
T1	1538960	41	0	0
T2	0	4	0	0
T4	383296	0	0	0
T5	10212	18	0	0
T6	148428	0	0	0
T9	0	9	0	0
T10	0	98	0	0
T11	0	105	0	0
T13	0	18	0	0
T15	0	85	0	0
T16	6048	0	0	0
T17	10068	0	0	0
T18	14860	17	0	0
T23	9060	0	0	0
T24	6152	0	0	0
T25	6852	0	0	0
T26	0	26	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	209076356	2213	0	0
TransStop_A	209076356	1167	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209076356	2213	0	0
T1	384740	20	0	0
T2	0	2	0	0
T4	95824	0	0	0
T5	2553	6	0	0
T6	37107	0	0	0
T9	0	6	0	0
T10	0	62	0	0
T11	0	47	0	0
T13	0	5	0	0
T15	0	42	0	0
T16	1512	0	0	0
T17	2517	0	0	0
T18	3715	9	0	0
T23	2265	0	0	0
T24	1538	0	0	0
T25	1713	0	0	0
T26	0	12	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209076356	1167	0	0
T1	384740	9	0	0
T2	0	1	0	0
T4	95824	0	0	0
T5	2553	4	0	0
T6	37107	0	0	0
T9	0	2	0	0
T10	0	29	0	0
T11	0	29	0	0
T13	0	3	0	0
T15	0	21	0	0
T16	1512	0	0	0
T17	2517	0	0	0
T18	3715	5	0	0
T23	2265	0	0	0
T24	1538	0	0	0
T25	1713	0	0	0
T26	0	7	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	209076356	2160	0	0
TransStop_A	209076356	1125	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209076356	2160	0	0
T1	384740	23	0	0
T2	0	2	0	0
T4	95824	0	0	0
T5	2553	8	0	0
T6	37107	0	0	0
T9	0	6	0	0
T10	0	55	0	0
T11	0	50	0	0
T13	0	8	0	0
T15	0	35	0	0
T16	1512	0	0	0
T17	2517	0	0	0
T18	3715	9	0	0
T23	2265	0	0	0
T24	1538	0	0	0
T25	1713	0	0	0
T26	0	11	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209076356	1125	0	0
T1	384740	15	0	0
T2	0	1	0	0
T4	95824	0	0	0
T5	2553	6	0	0
T6	37107	0	0	0
T9	0	2	0	0
T10	0	22	0	0
T11	0	23	0	0
T13	0	5	0	0
T15	0	17	0	0
T16	1512	0	0	0
T17	2517	0	0	0
T18	3715	3	0	0
T23	2265	0	0	0
T24	1538	0	0	0
T25	1713	0	0	0
T26	0	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	209076356	2156	0	0
TransStop_A	209076356	1136	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209076356	2156	0	0
T1	384740	16	0	0
T2	0	2	0	0
T4	95824	0	0	0
T5	2553	8	0	0
T6	37107	0	0	0
T9	0	8	0	0
T10	0	61	0	0
T11	0	47	0	0
T13	0	10	0	0
T15	0	42	0	0
T16	1512	0	0	0
T17	2517	0	0	0
T18	3715	8	0	0
T23	2265	0	0	0
T24	1538	0	0	0
T25	1713	0	0	0
T26	0	13	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209076356	1136	0	0
T1	384740	5	0	0
T2	0	1	0	0
T4	95824	0	0	0
T5	2553	4	0	0
T6	37107	0	0	0
T9	0	3	0	0
T10	0	24	0	0
T11	0	26	0	0
T13	0	6	0	0
T15	0	21	0	0
T16	1512	0	0	0
T17	2517	0	0	0
T18	3715	4	0	0
T23	2265	0	0	0
T24	1538	0	0	0
T25	1713	0	0	0
T26	0	7	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	209076356	2169	0	0
TransStop_A	209076356	1143	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209076356	2169	0	0
T1	384740	24	0	0
T2	0	2	0	0
T4	95824	0	0	0
T5	2553	8	0	0
T6	37107	0	0	0
T9	0	7	0	0
T10	0	62	0	0
T11	0	51	0	0
T13	0	6	0	0
T15	0	41	0	0
T16	1512	0	0	0
T17	2517	0	0	0
T18	3715	9	0	0
T23	2265	0	0	0
T24	1538	0	0	0
T25	1713	0	0	0
T26	0	10	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209076356	1143	0	0
T1	384740	12	0	0
T2	0	1	0	0
T4	95824	0	0	0
T5	2553	4	0	0
T6	37107	0	0	0
T9	0	2	0	0
T10	0	23	0	0
T11	0	27	0	0
T13	0	4	0	0
T15	0	26	0	0
T16	1512	0	0	0
T17	2517	0	0	0
T18	3715	5	0	0
T23	2265	0	0	0
T24	1538	0	0	0
T25	1713	0	0	0
T26	0	6	0	0