Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	68725620	6192299	0	60

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68725620	6192299	0	60
T1	170080	276688	0	0
T2	172186	7551	0	1
T3	53372	24204	0	1
T9	0	4225	0	0
T10	0	500814	0	0
T11	0	280996	0	0
T12	0	12540	0	1
T13	0	32193	0	0
T14	0	12629	0	1
T15	0	4555	0	1
T16	1467	0	0	0
T17	2493	0	0	0
T18	2490	0	0	0
T19	1512	0	0	0
T20	26569	0	0	0
T21	1036	0	0	0
T22	1100	0	0	0
T27	0	0	0	1
T28	0	0	0	1
T31	0	0	0	1
T102	0	0	0	1
T103	0	0	0	1