Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	69683759	1753715	0	0
clk_enables_rd_A	69683759	20926	0	0
clk_hints_rd_A	69683759	18966	0	0
extclk_ctrl_rd_A	69683759	23304	0	0
extclk_ctrl_regwen_rd_A	69683759	17533	0	0
jitter_enable_rd_A	69683759	27811	0	0
jitter_regwen_rd_A	69683759	18937	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	69683759	1753715	0	0
T1	170080	82571	0	0
T2	172186	0	0	0
T3	53372	0	0	0
T10	0	73487	0	0
T11	0	35868	0	0
T16	1467	0	0	0
T17	2493	0	0	0
T18	2490	0	0	0
T19	1512	0	0	0
T20	26569	0	0	0
T21	1036	0	0	0
T22	1100	0	0	0
T29	0	116658	0	0
T54	0	104981	0	0
T55	0	92425	0	0
T56	0	76475	0	0
T57	0	47458	0	0
T58	0	31540	0	0
T59	0	181978	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	69683759	20926	0	0
T11	129408	1330	0	0
T12	56237	0	0	0
T13	469581	0	0	0
T14	68748	0	0	0
T15	100316	0	0	0
T33	0	3	0	0
T37	1513	0	0	0
T38	1381	0	0	0
T55	0	3507	0	0
T56	0	1539	0	0
T58	0	1375	0	0
T60	2332	0	0	0
T61	40422	0	0	0
T104	1421	0	0	0
T127	0	4	0	0
T128	0	5	0	0
T129	0	8	0	0
T130	0	3	0	0
T131	0	1	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	69683759	18966	0	0
T11	129408	1296	0	0
T12	56237	0	0	0
T13	469581	0	0	0
T14	68748	0	0	0
T15	100316	0	0	0
T33	0	2	0	0
T37	1513	0	0	0
T38	1381	0	0	0
T55	0	3321	0	0
T56	0	1386	0	0
T58	0	1136	0	0
T60	2332	0	0	0
T61	40422	0	0	0
T104	1421	0	0	0
T127	0	5	0	0
T128	0	7	0	0
T129	0	5	0	0
T130	0	2	0	0
T132	0	7	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	69683759	23304	0	0
T9	35813	0	0	0
T11	0	1748	0	0
T19	1512	25	0	0
T20	26569	112	0	0
T21	1036	0	0	0
T22	1100	0	0	0
T30	102161	116	0	0
T36	1125	0	0	0
T72	0	1	0	0
T73	0	16	0	0
T98	1235	0	0	0
T99	1358	0	0	0
T133	0	76	0	0
T134	0	65	0	0
T135	0	30	0	0
T136	0	21	0	0
T137	1489	0	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	69683759	17533	0	0
T9	35813	0	0	0
T11	0	1277	0	0
T20	26569	37	0	0
T21	1036	0	0	0
T22	1100	0	0	0
T30	102161	73	0	0
T36	1125	0	0	0
T55	0	3018	0	0
T56	0	1436	0	0
T98	1235	0	0	0
T99	1358	0	0	0
T100	2020	0	0	0
T133	0	35	0	0
T134	0	21	0	0
T137	1489	0	0	0
T138	0	12	0	0
T139	0	41	0	0
T140	0	51	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	69683759	27811	0	0
T11	129408	2415	0	0
T12	56237	0	0	0
T13	469581	0	0	0
T14	68748	0	0	0
T15	100316	0	0	0
T33	0	111	0	0
T37	1513	0	0	0
T38	1381	0	0	0
T55	0	4059	0	0
T56	0	1418	0	0
T60	2332	0	0	0
T61	40422	0	0	0
T104	1421	0	0	0
T127	0	107	0	0
T128	0	87	0	0
T129	0	64	0	0
T130	0	130	0	0
T132	0	109	0	0
T141	0	74	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	69683759	18937	0	0
T11	129408	1490	0	0
T12	56237	0	0	0
T13	469581	0	0	0
T14	68748	0	0	0
T15	100316	0	0	0
T35	0	2959	0	0
T37	1513	0	0	0
T38	1381	0	0	0
T43	0	103	0	0
T55	0	3644	0	0
T56	0	1561	0	0
T58	0	1382	0	0
T60	2332	0	0	0
T61	40422	0	0	0
T89	0	34	0	0
T104	1421	0	0	0
T142	0	1532	0	0
T143	0	2094	0	0
T144	0	1294	0	0