Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	206176860	411	0	0
StatusRise_A	206176860	411	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206176860	411	0	0
T9	107439	0	0	0
T10	629487	0	0	0
T11	388224	0	0	0
T36	3375	9	0	0
T37	0	6	0	0
T38	0	17	0	0
T98	3705	0	0	0
T99	4074	0	0	0
T100	6060	0	0	0
T101	3834	0	0	0
T104	4263	0	0	0
T137	4467	0	0	0
T145	0	5	0	0
T146	0	17	0	0
T147	0	15	0	0
T148	0	9	0	0
T149	0	6	0	0
T150	0	5	0	0
T151	0	14	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206176860	411	0	0
T9	107439	0	0	0
T10	629487	0	0	0
T11	388224	0	0	0
T36	3375	9	0	0
T37	0	6	0	0
T38	0	17	0	0
T98	3705	0	0	0
T99	4074	0	0	0
T100	6060	0	0	0
T101	3834	0	0	0
T104	4263	0	0	0
T137	4467	0	0	0
T145	0	5	0	0
T146	0	17	0	0
T147	0	15	0	0
T148	0	9	0	0
T149	0	6	0	0
T150	0	5	0	0
T151	0	14	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	68725620	137	0	0
StatusRise_A	68725620	137	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68725620	137	0	0
T9	35813	0	0	0
T10	209829	0	0	0
T11	129408	0	0	0
T36	1125	2	0	0
T37	0	2	0	0
T38	0	5	0	0
T98	1235	0	0	0
T99	1358	0	0	0
T100	2020	0	0	0
T101	1278	0	0	0
T104	1421	0	0	0
T137	1489	0	0	0
T145	0	1	0	0
T146	0	6	0	0
T147	0	6	0	0
T148	0	3	0	0
T149	0	2	0	0
T150	0	2	0	0
T151	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68725620	137	0	0
T9	35813	0	0	0
T10	209829	0	0	0
T11	129408	0	0	0
T36	1125	2	0	0
T37	0	2	0	0
T38	0	5	0	0
T98	1235	0	0	0
T99	1358	0	0	0
T100	2020	0	0	0
T101	1278	0	0	0
T104	1421	0	0	0
T137	1489	0	0	0
T145	0	1	0	0
T146	0	6	0	0
T147	0	6	0	0
T148	0	3	0	0
T149	0	2	0	0
T150	0	2	0	0
T151	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	68725620	134	0	0
StatusRise_A	68725620	134	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68725620	134	0	0
T9	35813	0	0	0
T10	209829	0	0	0
T11	129408	0	0	0
T36	1125	3	0	0
T37	0	2	0	0
T38	0	6	0	0
T98	1235	0	0	0
T99	1358	0	0	0
T100	2020	0	0	0
T101	1278	0	0	0
T104	1421	0	0	0
T137	1489	0	0	0
T145	0	2	0	0
T146	0	6	0	0
T147	0	5	0	0
T148	0	3	0	0
T149	0	2	0	0
T150	0	1	0	0
T151	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68725620	134	0	0
T9	35813	0	0	0
T10	209829	0	0	0
T11	129408	0	0	0
T36	1125	3	0	0
T37	0	2	0	0
T38	0	6	0	0
T98	1235	0	0	0
T99	1358	0	0	0
T100	2020	0	0	0
T101	1278	0	0	0
T104	1421	0	0	0
T137	1489	0	0	0
T145	0	2	0	0
T146	0	6	0	0
T147	0	5	0	0
T148	0	3	0	0
T149	0	2	0	0
T150	0	1	0	0
T151	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	68725620	140	0	0
StatusRise_A	68725620	140	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68725620	140	0	0
T9	35813	0	0	0
T10	209829	0	0	0
T11	129408	0	0	0
T36	1125	4	0	0
T37	0	2	0	0
T38	0	6	0	0
T98	1235	0	0	0
T99	1358	0	0	0
T100	2020	0	0	0
T101	1278	0	0	0
T104	1421	0	0	0
T137	1489	0	0	0
T145	0	2	0	0
T146	0	5	0	0
T147	0	4	0	0
T148	0	3	0	0
T149	0	2	0	0
T150	0	2	0	0
T151	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68725620	140	0	0
T9	35813	0	0	0
T10	209829	0	0	0
T11	129408	0	0	0
T36	1125	4	0	0
T37	0	2	0	0
T38	0	6	0	0
T98	1235	0	0	0
T99	1358	0	0	0
T100	2020	0	0	0
T101	1278	0	0	0
T104	1421	0	0	0
T137	1489	0	0	0
T145	0	2	0	0
T146	0	5	0	0
T147	0	4	0	0
T148	0	3	0	0
T149	0	2	0	0
T150	0	2	0	0
T151	0	5	0	0