Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T1
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	31037	0	0
CgEnOn_A	2147483647	22135	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	31037	0	0
T1	3183124	173	0	0
T2	0	2	0	0
T4	559601	45	0	0
T5	15671	9	0	0
T6	222662	303	0	0
T9	2228703	0	0	0
T10	3087722	0	0	0
T11	3959495	0	0	0
T16	9269	15	0	0
T17	15588	3	0	0
T18	22856	12	0	0
T23	13993	3	0	0
T24	9371	3	0	0
T25	10523	3	0	0
T36	20425	17	0	0
T37	0	12	0	0
T38	0	30	0	0
T98	5960	0	0	0
T99	6403	0	0	0
T100	37187	0	0	0
T101	25234	0	0	0
T104	13909	0	0	0
T137	7048	0	0	0
T145	0	10	0	0
T146	0	30	0	0
T147	0	25	0	0
T148	0	15	0	0
T149	0	10	0	0
T150	0	5	0	0
T151	0	20	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	22135	0	0
T1	1845666	158	0	0
T2	507674	8	0	0
T3	93362	0	0	0
T5	2552	6	0	0
T9	995424	12	0	0
T10	2561677	199	0	0
T11	1838401	250	0	0
T13	0	5	0	0
T16	4011	12	0	0
T17	6829	0	0	0
T18	9928	9	0	0
T19	17787	0	0	0
T20	152251	0	0	0
T21	6875	10	0	0
T22	7820	0	0	0
T36	9204	26	0	0
T37	0	18	0	0
T38	0	30	0	0
T98	2769	0	0	0
T99	2966	0	0	0
T100	17914	0	0	0
T101	13915	0	0	0
T104	6568	0	0	0
T137	3199	10	0	0
T145	0	10	0	0
T146	0	30	0	0
T147	0	25	0	0
T148	0	15	0	0
T149	0	10	0	0
T150	0	5	0	0
T151	0	20	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T1
1	0	Unreachable
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	96924187	138	0	0
CgEnOn_A	96924187	138	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96924187	138	0	0
T9	222454	0	0	0
T10	948576	0	0	0
T11	408692	0	0	0
T36	2025	3	0	0
T37	0	2	0	0
T38	0	6	0	0
T98	613	0	0	0
T99	655	0	0	0
T100	4183	0	0	0
T101	3813	0	0	0
T104	1492	0	0	0
T137	684	0	0	0
T145	0	2	0	0
T146	0	6	0	0
T147	0	5	0	0
T148	0	3	0	0
T149	0	2	0	0
T150	0	1	0	0
T151	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96924187	138	0	0
T9	222454	0	0	0
T10	948576	0	0	0
T11	408692	0	0	0
T36	2025	3	0	0
T37	0	2	0	0
T38	0	6	0	0
T98	613	0	0	0
T99	655	0	0	0
T100	4183	0	0	0
T101	3813	0	0	0
T104	1492	0	0	0
T137	684	0	0	0
T145	0	2	0	0
T146	0	6	0	0
T147	0	5	0	0
T148	0	3	0	0
T149	0	2	0	0
T150	0	1	0	0
T151	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T1
1	0	Unreachable
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	48461731	138	0	0
CgEnOn_A	48461731	138	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48461731	138	0	0
T9	111226	0	0	0
T10	474285	0	0	0
T11	204345	0	0	0
T36	1012	3	0	0
T37	0	2	0	0
T38	0	6	0	0
T98	307	0	0	0
T99	327	0	0	0
T100	2090	0	0	0
T101	1907	0	0	0
T104	745	0	0	0
T137	342	0	0	0
T145	0	2	0	0
T146	0	6	0	0
T147	0	5	0	0
T148	0	3	0	0
T149	0	2	0	0
T150	0	1	0	0
T151	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48461731	138	0	0
T9	111226	0	0	0
T10	474285	0	0	0
T11	204345	0	0	0
T36	1012	3	0	0
T37	0	2	0	0
T38	0	6	0	0
T98	307	0	0	0
T99	327	0	0	0
T100	2090	0	0	0
T101	1907	0	0	0
T104	745	0	0	0
T137	342	0	0	0
T145	0	2	0	0
T146	0	6	0	0
T147	0	5	0	0
T148	0	3	0	0
T149	0	2	0	0
T150	0	1	0	0
T151	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T1
1	0	Unreachable
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	48461731	138	0	0
CgEnOn_A	48461731	138	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48461731	138	0	0
T9	111226	0	0	0
T10	474285	0	0	0
T11	204345	0	0	0
T36	1012	3	0	0
T37	0	2	0	0
T38	0	6	0	0
T98	307	0	0	0
T99	327	0	0	0
T100	2090	0	0	0
T101	1907	0	0	0
T104	745	0	0	0
T137	342	0	0	0
T145	0	2	0	0
T146	0	6	0	0
T147	0	5	0	0
T148	0	3	0	0
T149	0	2	0	0
T150	0	1	0	0
T151	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48461731	138	0	0
T9	111226	0	0	0
T10	474285	0	0	0
T11	204345	0	0	0
T36	1012	3	0	0
T37	0	2	0	0
T38	0	6	0	0
T98	307	0	0	0
T99	327	0	0	0
T100	2090	0	0	0
T101	1907	0	0	0
T104	745	0	0	0
T137	342	0	0	0
T145	0	2	0	0
T146	0	6	0	0
T147	0	5	0	0
T148	0	3	0	0
T149	0	2	0	0
T150	0	1	0	0
T151	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T1
1	0	Unreachable
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	48461731	138	0	0
CgEnOn_A	48461731	138	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48461731	138	0	0
T9	111226	0	0	0
T10	474285	0	0	0
T11	204345	0	0	0
T36	1012	3	0	0
T37	0	2	0	0
T38	0	6	0	0
T98	307	0	0	0
T99	327	0	0	0
T100	2090	0	0	0
T101	1907	0	0	0
T104	745	0	0	0
T137	342	0	0	0
T145	0	2	0	0
T146	0	6	0	0
T147	0	5	0	0
T148	0	3	0	0
T149	0	2	0	0
T150	0	1	0	0
T151	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48461731	138	0	0
T9	111226	0	0	0
T10	474285	0	0	0
T11	204345	0	0	0
T36	1012	3	0	0
T37	0	2	0	0
T38	0	6	0	0
T98	307	0	0	0
T99	327	0	0	0
T100	2090	0	0	0
T101	1907	0	0	0
T104	745	0	0	0
T137	342	0	0	0
T145	0	2	0	0
T146	0	6	0	0
T147	0	5	0	0
T148	0	3	0	0
T149	0	2	0	0
T150	0	1	0	0
T151	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T1
1	0	Unreachable
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	195408231	138	0	0
CgEnOn_A	195408231	135	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195408231	138	0	0
T9	439292	0	0	0
T10	190246	0	0	0
T11	816674	0	0	0
T36	4143	3	0	0
T37	0	2	0	0
T38	0	6	0	0
T98	1235	0	0	0
T99	1330	0	0	0
T100	7461	0	0	0
T101	4381	0	0	0
T104	2841	0	0	0
T137	1489	0	0	0
T145	0	2	0	0
T146	0	6	0	0
T147	0	5	0	0
T148	0	3	0	0
T149	0	2	0	0
T150	0	1	0	0
T151	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195408231	135	0	0
T9	439292	0	0	0
T10	190246	0	0	0
T11	816674	0	0	0
T36	4143	3	0	0
T37	0	2	0	0
T38	0	6	0	0
T98	1235	0	0	0
T99	1330	0	0	0
T100	7461	0	0	0
T101	4381	0	0	0
T104	2841	0	0	0
T137	1489	0	0	0
T145	0	2	0	0
T146	0	6	0	0
T147	0	5	0	0
T148	0	3	0	0
T149	0	2	0	0
T150	0	1	0	0
T151	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T1
1	0	Unreachable
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	209075936	137	0	0
CgEnOn_A	209075936	137	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209075936	137	0	0
T9	499611	0	0	0
T10	212579	0	0	0
T11	854929	0	0	0
T36	4573	2	0	0
T37	0	2	0	0
T38	0	5	0	0
T98	1287	0	0	0
T99	1386	0	0	0
T100	7771	0	0	0
T101	4564	0	0	0
T104	2960	0	0	0
T137	1552	0	0	0
T145	0	1	0	0
T146	0	6	0	0
T147	0	6	0	0
T148	0	3	0	0
T149	0	2	0	0
T150	0	2	0	0
T151	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209075936	137	0	0
T9	499611	0	0	0
T10	212579	0	0	0
T11	854929	0	0	0
T36	4573	2	0	0
T37	0	2	0	0
T38	0	5	0	0
T98	1287	0	0	0
T99	1386	0	0	0
T100	7771	0	0	0
T101	4564	0	0	0
T104	2960	0	0	0
T137	1552	0	0	0
T145	0	1	0	0
T146	0	6	0	0
T147	0	6	0	0
T148	0	3	0	0
T149	0	2	0	0
T150	0	2	0	0
T151	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T1
1	0	Unreachable
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	209075936	137	0	0
CgEnOn_A	209075936	137	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209075936	137	0	0
T9	499611	0	0	0
T10	212579	0	0	0
T11	854929	0	0	0
T36	4573	2	0	0
T37	0	2	0	0
T38	0	5	0	0
T98	1287	0	0	0
T99	1386	0	0	0
T100	7771	0	0	0
T101	4564	0	0	0
T104	2960	0	0	0
T137	1552	0	0	0
T145	0	1	0	0
T146	0	6	0	0
T147	0	6	0	0
T148	0	3	0	0
T149	0	2	0	0
T150	0	2	0	0
T151	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209075936	137	0	0
T9	499611	0	0	0
T10	212579	0	0	0
T11	854929	0	0	0
T36	4573	2	0	0
T37	0	2	0	0
T38	0	5	0	0
T98	1287	0	0	0
T99	1386	0	0	0
T100	7771	0	0	0
T101	4564	0	0	0
T104	2960	0	0	0
T137	1552	0	0	0
T145	0	1	0	0
T146	0	6	0	0
T147	0	6	0	0
T148	0	3	0	0
T149	0	2	0	0
T150	0	2	0	0
T151	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T1
1	0	Unreachable
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	100343035	140	0	0
CgEnOn_A	100343035	140	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100343035	140	0	0
T9	234057	0	0	0
T10	100887	0	0	0
T11	411236	0	0	0
T36	2075	4	0	0
T37	0	2	0	0
T38	0	6	0	0
T98	617	0	0	0
T99	665	0	0	0
T100	3731	0	0	0
T101	2191	0	0	0
T104	1421	0	0	0
T137	745	0	0	0
T145	0	2	0	0
T146	0	5	0	0
T147	0	4	0	0
T148	0	3	0	0
T149	0	2	0	0
T150	0	2	0	0
T151	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100343035	140	0	0
T9	234057	0	0	0
T10	100887	0	0	0
T11	411236	0	0	0
T36	2075	4	0	0
T37	0	2	0	0
T38	0	6	0	0
T98	617	0	0	0
T99	665	0	0	0
T100	3731	0	0	0
T101	2191	0	0	0
T104	1421	0	0	0
T137	745	0	0	0
T145	0	2	0	0
T146	0	5	0	0
T147	0	4	0	0
T148	0	3	0	0
T149	0	2	0	0
T150	0	2	0	0
T151	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	48461731	5168	0	0
CgEnOn_A	48461731	2945	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48461731	5168	0	0
T1	913016	50	0	0
T4	12777	15	0	0
T5	596	1	0	0
T6	6934	101	0	0
T16	350	5	0	0
T17	631	1	0	0
T18	882	1	0	0
T23	558	1	0	0
T24	335	1	0	0
T25	402	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48461731	2945	0	0
T1	913016	45	0	0
T2	72468	2	0	0
T3	13330	0	0	0
T9	0	2	0	0
T10	0	46	0	0
T11	0	68	0	0
T16	350	4	0	0
T17	631	0	0	0
T18	882	0	0	0
T19	2701	0	0	0
T20	16743	0	0	0
T21	965	3	0	0
T22	1139	0	0	0
T36	0	3	0	0
T37	0	2	0	0
T137	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	96924187	5180	0	0
CgEnOn_A	96924187	2957	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96924187	5180	0	0
T1	182603	55	0	0
T4	25549	15	0	0
T5	1192	1	0	0
T6	13872	101	0	0
T16	699	5	0	0
T17	1264	1	0	0
T18	1764	1	0	0
T23	1118	1	0	0
T24	671	1	0	0
T25	803	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	96924187	2957	0	0
T1	182603	50	0	0
T2	144938	2	0	0
T3	26660	0	0	0
T9	0	2	0	0
T10	0	46	0	0
T11	0	67	0	0
T16	699	4	0	0
T17	1264	0	0	0
T18	1764	0	0	0
T19	5405	0	0	0
T20	33484	0	0	0
T21	1930	3	0	0
T22	2278	0	0	0
T36	0	3	0	0
T37	0	2	0	0
T137	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	195408231	5159	0	0
CgEnOn_A	195408231	2933	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195408231	5159	0	0
T1	365307	48	0	0
T4	91987	15	0	0
T5	2450	1	0	0
T6	35621	101	0	0
T16	1451	5	0	0
T17	2417	1	0	0
T18	3567	1	0	0
T23	2174	1	0	0
T24	1476	1	0	0
T25	1644	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195408231	2933	0	0
T1	365307	43	0	0
T2	290268	2	0	0
T3	53372	0	0	0
T9	0	2	0	0
T10	0	45	0	0
T11	0	68	0	0
T16	1451	4	0	0
T17	2417	0	0	0
T18	3567	0	0	0
T19	9681	0	0	0
T20	102024	0	0	0
T21	3980	4	0	0
T22	4403	0	0	0
T36	0	3	0	0
T37	0	2	0	0
T137	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T5,T6,T4
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	100343035	5180	0	0
CgEnOn_A	100343035	2953	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100343035	5180	0	0
T1	183238	49	0	0
T4	45996	15	0	0
T5	1225	1	0	0
T6	17811	101	0	0
T16	725	4	0	0
T17	1208	1	0	0
T18	1783	1	0	0
T23	1087	1	0	0
T24	737	1	0	0
T25	822	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100343035	2953	0	0
T1	183238	44	0	0
T2	159541	2	0	0
T3	26687	0	0	0
T9	0	2	0	0
T10	0	46	0	0
T11	0	65	0	0
T16	725	3	0	0
T17	1208	0	0	0
T18	1783	0	0	0
T19	4840	0	0	0
T20	51015	0	0	0
T21	1990	4	0	0
T22	2201	0	0	0
T36	0	4	0	0
T37	0	2	0	0
T137	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T1
1	0	Covered	T5,T1,T18
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	209075936	2350	0	0
CgEnOn_A	209075936	2350	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209075936	2350	0	0
T1	384740	20	0	0
T2	0	2	0	0
T4	95823	0	0	0
T5	2552	6	0	0
T6	37106	0	0	0
T9	0	6	0	0
T10	0	62	0	0
T11	0	47	0	0
T13	0	5	0	0
T16	1511	0	0	0
T17	2517	0	0	0
T18	3715	9	0	0
T23	2264	0	0	0
T24	1538	0	0	0
T25	1713	0	0	0
T36	0	2	0	0
T37	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209075936	2350	0	0
T1	384740	20	0	0
T2	0	2	0	0
T4	95823	0	0	0
T5	2552	6	0	0
T6	37106	0	0	0
T9	0	6	0	0
T10	0	62	0	0
T11	0	47	0	0
T13	0	5	0	0
T16	1511	0	0	0
T17	2517	0	0	0
T18	3715	9	0	0
T23	2264	0	0	0
T24	1538	0	0	0
T25	1713	0	0	0
T36	0	2	0	0
T37	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T1
1	0	Covered	T5,T1,T18
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	209075936	2297	0	0
CgEnOn_A	209075936	2297	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209075936	2297	0	0
T1	384740	23	0	0
T2	0	2	0	0
T4	95823	0	0	0
T5	2552	8	0	0
T6	37106	0	0	0
T9	0	6	0	0
T10	0	55	0	0
T11	0	50	0	0
T13	0	8	0	0
T16	1511	0	0	0
T17	2517	0	0	0
T18	3715	9	0	0
T23	2264	0	0	0
T24	1538	0	0	0
T25	1713	0	0	0
T36	0	2	0	0
T37	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209075936	2297	0	0
T1	384740	23	0	0
T2	0	2	0	0
T4	95823	0	0	0
T5	2552	8	0	0
T6	37106	0	0	0
T9	0	6	0	0
T10	0	55	0	0
T11	0	50	0	0
T13	0	8	0	0
T16	1511	0	0	0
T17	2517	0	0	0
T18	3715	9	0	0
T23	2264	0	0	0
T24	1538	0	0	0
T25	1713	0	0	0
T36	0	2	0	0
T37	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T1
1	0	Covered	T5,T1,T18
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	209075936	2293	0	0
CgEnOn_A	209075936	2293	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209075936	2293	0	0
T1	384740	16	0	0
T2	0	2	0	0
T4	95823	0	0	0
T5	2552	8	0	0
T6	37106	0	0	0
T9	0	8	0	0
T10	0	61	0	0
T11	0	47	0	0
T13	0	10	0	0
T16	1511	0	0	0
T17	2517	0	0	0
T18	3715	8	0	0
T23	2264	0	0	0
T24	1538	0	0	0
T25	1713	0	0	0
T36	0	2	0	0
T37	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209075936	2293	0	0
T1	384740	16	0	0
T2	0	2	0	0
T4	95823	0	0	0
T5	2552	8	0	0
T6	37106	0	0	0
T9	0	8	0	0
T10	0	61	0	0
T11	0	47	0	0
T13	0	10	0	0
T16	1511	0	0	0
T17	2517	0	0	0
T18	3715	8	0	0
T23	2264	0	0	0
T24	1538	0	0	0
T25	1713	0	0	0
T36	0	2	0	0
T37	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T1
1	0	Covered	T5,T1,T18
1	1	Covered	T5,T6,T4

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	209075936	2306	0	0
CgEnOn_A	209075936	2306	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209075936	2306	0	0
T1	384740	24	0	0
T2	0	2	0	0
T4	95823	0	0	0
T5	2552	8	0	0
T6	37106	0	0	0
T9	0	7	0	0
T10	0	62	0	0
T11	0	51	0	0
T13	0	6	0	0
T16	1511	0	0	0
T17	2517	0	0	0
T18	3715	9	0	0
T23	2264	0	0	0
T24	1538	0	0	0
T25	1713	0	0	0
T36	0	2	0	0
T37	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209075936	2306	0	0
T1	384740	24	0	0
T2	0	2	0	0
T4	95823	0	0	0
T5	2552	8	0	0
T6	37106	0	0	0
T9	0	7	0	0
T10	0	62	0	0
T11	0	51	0	0
T13	0	6	0	0
T16	1511	0	0	0
T17	2517	0	0	0
T18	3715	9	0	0
T23	2264	0	0	0
T24	1538	0	0	0
T25	1713	0	0	0
T36	0	2	0	0
T37	0	2	0	0