Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	284690	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1233302

1

T5

30

T6

50

T1

106

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	389588	1			T5	36		T6	72		T1	28
values[0x0]	522833	1			T5	19		T6	19		T1	106
values[0x1]	605571	1			T5	8		T6	35		T1	106

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	173119	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1344873

1

T5

35

T6

61

T1

145

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5623	1			T1	1		T8	2		T9	4
valid_sources[0x01]	6505	1			T1	2		T8	4		T9	33
valid_sources[0x02]	6330	1			T1	2		T8	2		T9	10
valid_sources[0x03]	5881	1			T1	2		T8	5		T9	10
valid_sources[0x04]	5756	1			T5	1		T1	1		T8	5
valid_sources[0x05]	6442	1			T8	1		T9	14		T10	2
valid_sources[0x06]	5808	1			T1	1		T16	2		T8	3
valid_sources[0x07]	5458	1			T1	3		T8	3		T9	14
valid_sources[0x08]	5431	1			T5	1		T8	1		T9	23
valid_sources[0x09]	6260	1			T6	1		T1	1		T16	4
valid_sources[0x0a]	6405	1			T1	1		T16	2		T27	1
valid_sources[0x0b]	5367	1			T1	1		T35	5		T33	3
valid_sources[0x0c]	5997	1			T6	2		T1	1		T123	1
valid_sources[0x0d]	5614	1			T1	1		T27	1		T9	14
valid_sources[0x0e]	5150	1			T1	1		T8	5		T9	16
valid_sources[0x0f]	5616	1			T5	1		T1	3		T8	1
valid_sources[0x10]	6927	1			T1	1		T27	1		T8	2
valid_sources[0x11]	5827	1			T5	1		T16	1		T8	4
valid_sources[0x12]	5567	1			T8	5		T9	13		T23	1
valid_sources[0x13]	5659	1			T5	1		T1	2		T8	6
valid_sources[0x14]	6081	1			T1	1		T123	1		T8	4
valid_sources[0x15]	5527	1			T5	1		T6	7		T1	2
valid_sources[0x16]	5667	1			T31	2		T8	2		T9	29
valid_sources[0x17]	5864	1			T1	2		T26	6		T9	15
valid_sources[0x18]	5738	1			T16	1		T27	1		T178	1
valid_sources[0x19]	5530	1			T6	5		T1	1		T16	7
valid_sources[0x1a]	5994	1			T1	4		T123	1		T8	4
valid_sources[0x1b]	5429	1			T1	3		T21	1		T8	2
valid_sources[0x1c]	6486	1			T8	1		T9	8		T23	1
valid_sources[0x1d]	5721	1			T8	2		T9	2		T10	2
valid_sources[0x1e]	5818	1			T5	1		T1	1		T15	1
valid_sources[0x1f]	5704	1			T6	7		T1	1		T21	1
valid_sources[0x20]	5927	1			T5	1		T6	1		T22	6
valid_sources[0x21]	6060	1			T8	1		T9	6		T23	2
valid_sources[0x22]	6178	1			T1	2		T16	1		T27	1
valid_sources[0x23]	6039	1			T6	1		T1	1		T25	96
valid_sources[0x24]	7010	1			T1	1		T8	1		T9	28
valid_sources[0x25]	5500	1			T1	3		T8	2		T9	10
valid_sources[0x26]	5686	1			T1	1		T8	2		T9	5
valid_sources[0x27]	5909	1			T1	1		T30	1		T8	3
valid_sources[0x28]	5459	1			T6	2		T1	1		T8	1
valid_sources[0x29]	5853	1			T6	1		T1	2		T9	9
valid_sources[0x2a]	5695	1			T6	2		T1	1		T16	3
valid_sources[0x2b]	6255	1			T6	1		T1	2		T8	3
valid_sources[0x2c]	6088	1			T123	2		T8	2		T9	20
valid_sources[0x2d]	5771	1			T5	1		T1	1		T8	2
valid_sources[0x2e]	6328	1			T16	1		T21	1		T123	1
valid_sources[0x2f]	6192	1			T8	4		T9	13		T10	2
valid_sources[0x30]	6038	1			T20	1		T22	1		T30	4
valid_sources[0x31]	6213	1			T1	1		T9	6		T10	4
valid_sources[0x32]	6305	1			T1	2		T8	4		T9	8
valid_sources[0x33]	6166	1			T5	1		T6	1		T9	14
valid_sources[0x34]	6223	1			T1	1		T8	3		T9	9
valid_sources[0x35]	6019	1			T6	6		T1	1		T9	7
valid_sources[0x36]	7988	1			T6	4		T17	1		T2	2133
valid_sources[0x37]	5759	1			T1	1		T16	1		T22	2
valid_sources[0x38]	5734	1			T1	1		T26	2		T9	22
valid_sources[0x39]	6168	1			T16	2		T33	26		T8	4
valid_sources[0x3a]	5821	1			T6	2		T1	2		T8	1
valid_sources[0x3b]	5894	1			T5	1		T8	2		T9	16
valid_sources[0x3c]	6339	1			T1	3		T15	3		T16	1
valid_sources[0x3d]	6128	1			T16	2		T17	1		T178	3
valid_sources[0x3e]	5694	1			T6	2		T9	17		T124	2
valid_sources[0x3f]	7496	1			T1	1		T8	4		T9	11
valid_sources[0x40]	6142	1			T1	1		T9	43		T131	2
valid_sources[0x41]	5805	1			T1	2		T8	3		T9	8
valid_sources[0x42]	5414	1			T178	1		T8	3		T9	11
valid_sources[0x43]	6024	1			T6	1		T1	4		T31	3
valid_sources[0x44]	6286	1			T5	1		T8	2		T9	18
valid_sources[0x45]	5767	1			T8	3		T9	19		T124	1
valid_sources[0x46]	6632	1			T6	1		T20	2		T8	3
valid_sources[0x47]	5741	1			T8	2		T9	25		T10	2
valid_sources[0x48]	5985	1			T8	1		T9	8		T23	2
valid_sources[0x49]	5682	1			T5	2		T1	1		T16	1
valid_sources[0x4a]	5395	1			T1	1		T8	2		T9	12
valid_sources[0x4b]	5427	1			T1	2		T27	1		T8	2
valid_sources[0x4c]	5776	1			T1	1		T16	1		T8	3
valid_sources[0x4d]	6061	1			T1	1		T8	4		T9	11
valid_sources[0x4e]	6064	1			T16	1		T8	2		T9	17
valid_sources[0x4f]	5226	1			T6	3		T8	1		T9	2
valid_sources[0x50]	6550	1			T8	4		T9	12		T39	5
valid_sources[0x51]	6080	1			T1	3		T16	1		T27	1
valid_sources[0x52]	7957	1			T1	1		T16	2		T31	2
valid_sources[0x53]	6068	1			T5	2		T21	1		T27	1
valid_sources[0x54]	6645	1			T1	1		T178	1		T8	2
valid_sources[0x55]	6180	1			T16	4		T8	3		T9	13
valid_sources[0x56]	5729	1			T6	2		T1	2		T16	2
valid_sources[0x57]	5463	1			T1	1		T16	1		T27	2
valid_sources[0x58]	6198	1			T6	4		T1	1		T16	3
valid_sources[0x59]	5750	1			T5	1		T20	1		T8	5
valid_sources[0x5a]	6146	1			T20	3		T8	2		T9	2
valid_sources[0x5b]	6130	1			T1	1		T30	1		T123	1
valid_sources[0x5c]	5514	1			T1	1		T27	1		T8	3
valid_sources[0x5d]	6368	1			T6	1		T8	1		T9	8
valid_sources[0x5e]	5487	1			T5	1		T1	2		T27	1
valid_sources[0x5f]	5327	1			T21	1		T8	2		T9	9
valid_sources[0x60]	6790	1			T5	4		T1	1		T33	11
valid_sources[0x61]	5431	1			T1	2		T20	1		T8	1
valid_sources[0x62]	5700	1			T6	1		T15	3		T8	2
valid_sources[0x63]	7295	1			T6	2		T123	1		T9	14
valid_sources[0x64]	5579	1			T1	3		T27	1		T123	1
valid_sources[0x65]	5783	1			T1	1		T8	1		T9	27
valid_sources[0x66]	5831	1			T1	1		T22	1		T8	3
valid_sources[0x67]	5885	1			T6	1		T1	1		T8	1
valid_sources[0x68]	5611	1			T5	1		T1	4		T33	13
valid_sources[0x69]	5383	1			T8	3		T9	1		T23	1
valid_sources[0x6a]	5803	1			T8	2		T9	19		T10	2
valid_sources[0x6b]	5423	1			T1	1		T21	1		T8	1
valid_sources[0x6c]	5639	1			T21	1		T8	6		T9	11
valid_sources[0x6d]	6975	1			T6	3		T15	1		T27	1
valid_sources[0x6e]	6636	1			T5	1		T1	1		T31	7
valid_sources[0x6f]	5592	1			T8	4		T9	13		T124	1
valid_sources[0x70]	5979	1			T8	3		T9	11		T23	3
valid_sources[0x71]	6244	1			T123	1		T8	1		T9	12
valid_sources[0x72]	5213	1			T1	2		T27	2		T35	2
valid_sources[0x73]	5744	1			T5	2		T1	2		T178	1
valid_sources[0x74]	5872	1			T5	2		T6	1		T21	1
valid_sources[0x75]	5947	1			T31	1		T8	2		T9	27
valid_sources[0x76]	5345	1			T5	1		T1	1		T16	5
valid_sources[0x77]	5316	1			T5	2		T1	1		T15	1
valid_sources[0x78]	5534	1			T1	3		T15	1		T123	1
valid_sources[0x79]	5639	1			T16	9		T20	1		T27	1
valid_sources[0x7a]	6072	1			T1	2		T21	1		T30	2
valid_sources[0x7b]	5579	1			T1	2		T123	1		T8	5
valid_sources[0x7c]	5772	1			T1	1		T123	1		T9	8
valid_sources[0x7d]	6611	1			T1	1		T15	2		T8	4
valid_sources[0x7e]	6105	1			T1	1		T22	6		T8	5
valid_sources[0x7f]	5783	1			T123	3		T8	7		T9	11
valid_sources[0x80]	6084	1			T5	2		T8	5		T9	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

317230

1

T5

19

T6

38

T1

13

values[0x0]

all_enables

biggest_size

471834

1

T5

7

T6

7

T1

65

values[0x1]

all_enables

biggest_size

444238

1

T5

4

T6

5

T1

28