Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T19,T2,T25
0	1	Covered	T2,T25,T26
1	0	Covered	T5,T6,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T25,T26
1	0	Covered	T19,T28,T29
1	1	Covered	T5,T6,T1

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	524200183	7677	0	0
GateOpen_A	524200183	14017	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524200183	7677	0	0
T2	1666806	84	0	0
T3	0	84	0	0
T9	0	12	0	0
T19	5763	3	0	0
T20	36062	0	0	0
T21	2592	0	0	0
T22	11287	0	0	0
T25	84620	0	0	0
T26	3206	0	0	0
T27	18413	0	0	0
T28	3309	4	0	0
T29	3705	31	0	0
T30	808	0	0	0
T31	1121	0	0	0
T32	838	0	0	0
T35	1714	0	0	0
T43	0	11	0	0
T82	0	2	0	0
T124	0	4	0	0
T125	0	2	0	0
T178	0	6	0	0
T179	0	5	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	524200183	14017	0	0
T1	308593	0	0	0
T2	0	104	0	0
T4	243528	0	0	0
T5	11977	4	0	0
T6	11301	0	0	0
T15	3534	4	0	0
T16	5416	4	0	0
T17	4346	4	0	0
T18	23387	0	0	0
T19	7450	7	0	0
T20	46180	4	0	0
T25	0	4	0	0
T26	0	4	0	0
T27	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T19,T2,T25
0	1	Covered	T2,T25,T26
1	0	Covered	T5,T6,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T25,T26
1	0	Covered	T19,T28,T29
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	57714239	1850	0	0
GateOpen_A	57714239	3434	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57714239	1850	0	0
T2	183070	21	0	0
T3	0	19	0	0
T9	0	3	0	0
T19	814	1	0	0
T20	5275	0	0	0
T21	366	0	0	0
T22	1690	0	0	0
T25	8424	0	0	0
T26	348	0	0	0
T27	2284	0	0	0
T28	355	1	0	0
T29	400	8	0	0
T43	0	3	0	0
T82	0	1	0	0
T124	0	1	0	0
T178	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57714239	3434	0	0
T1	34275	0	0	0
T2	0	26	0	0
T4	24803	0	0	0
T5	1318	1	0	0
T6	1236	0	0	0
T15	375	1	0	0
T16	598	1	0	0
T17	481	1	0	0
T18	2588	0	0	0
T19	814	2	0	0
T20	5275	1	0	0
T25	0	1	0	0
T26	0	1	0	0
T27	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T19,T2,T25
0	1	Covered	T2,T25,T26
1	0	Covered	T5,T6,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T25,T26
1	0	Covered	T19,T28,T29
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	115428896	1939	0	0
GateOpen_A	115428896	3523	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115428896	1939	0	0
T2	366147	20	0	0
T3	0	21	0	0
T9	0	3	0	0
T19	1628	1	0	0
T20	10551	0	0	0
T21	733	0	0	0
T22	3379	0	0	0
T25	16848	0	0	0
T26	695	0	0	0
T27	4575	0	0	0
T28	710	1	0	0
T29	799	8	0	0
T43	0	3	0	0
T124	0	1	0	0
T125	0	1	0	0
T178	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115428896	3523	0	0
T1	68549	0	0	0
T2	0	25	0	0
T4	49606	0	0	0
T5	2635	1	0	0
T6	2471	0	0	0
T15	750	1	0	0
T16	1195	1	0	0
T17	962	1	0	0
T18	5175	0	0	0
T19	1628	2	0	0
T20	10551	1	0	0
T25	0	1	0	0
T26	0	1	0	0
T27	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T19,T2,T25
0	1	Covered	T2,T25,T26
1	0	Covered	T5,T6,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T25,T26
1	0	Covered	T19,T28,T29
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	232233984	1969	0	0
GateOpen_A	232233984	3555	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232233984	1969	0	0
T2	731607	23	0	0
T3	0	23	0	0
T9	0	3	0	0
T19	3321	1	0	0
T20	20236	0	0	0
T21	1493	0	0	0
T22	6218	0	0	0
T25	33805	0	0	0
T26	1442	0	0	0
T27	7703	0	0	0
T28	1498	1	0	0
T29	1690	8	0	0
T43	0	3	0	0
T124	0	1	0	0
T125	0	1	0	0
T178	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232233984	3555	0	0
T1	137177	0	0	0
T2	0	28	0	0
T4	99304	0	0	0
T5	5349	1	0	0
T6	5063	0	0	0
T15	1606	1	0	0
T16	2415	1	0	0
T17	1935	1	0	0
T18	10416	0	0	0
T19	3321	2	0	0
T20	20236	1	0	0
T25	0	1	0	0
T26	0	1	0	0
T27	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T2,T25,T28
0	1	Covered	T2,T25,T26
1	0	Covered	T5,T6,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T25,T26
1	0	Covered	T28,T29,T43
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	118823064	1919	0	0
GateOpen_A	118823064	3505	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118823064	1919	0	0
T2	385982	20	0	0
T3	0	21	0	0
T9	0	3	0	0
T25	25543	0	0	0
T26	721	0	0	0
T27	3851	0	0	0
T28	746	1	0	0
T29	816	7	0	0
T30	808	0	0	0
T31	1121	0	0	0
T32	838	0	0	0
T35	1714	0	0	0
T43	0	2	0	0
T82	0	1	0	0
T124	0	1	0	0
T178	0	1	0	0
T179	0	5	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118823064	3505	0	0
T1	68592	0	0	0
T2	0	25	0	0
T4	69815	0	0	0
T5	2675	1	0	0
T6	2531	0	0	0
T15	803	1	0	0
T16	1208	1	0	0
T17	968	1	0	0
T18	5208	0	0	0
T19	1687	1	0	0
T20	10118	1	0	0
T25	0	1	0	0
T26	0	1	0	0
T27	0	1	0	0