Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	350235300	38165	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	350235300	38165	0	0
T1	71445	73	0	0
T2	0	484	0	0
T3	0	113	0	0
T4	712685	0	0	0
T8	0	540	0	0
T9	0	459	0	0
T10	0	58	0	0
T11	0	89	0	0
T12	0	1136	0	0
T13	0	222	0	0
T14	0	108	0	0
T15	8360	0	0	0
T16	12070	0	0	0
T17	4840	0	0	0
T18	14645	0	0	0
T19	4210	0	0	0
T20	5265	0	0	0
T21	7625	0	0	0
T22	4530	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	70047060	5716	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70047060	5716	0	0
T1	14289	14	0	0
T2	0	72	0	0
T3	0	20	0	0
T4	142537	0	0	0
T8	0	80	0	0
T9	0	73	0	0
T10	0	9	0	0
T11	0	13	0	0
T12	0	155	0	0
T13	0	30	0	0
T14	0	15	0	0
T15	1672	0	0	0
T16	2414	0	0	0
T17	968	0	0	0
T18	2929	0	0	0
T19	842	0	0	0
T20	1053	0	0	0
T21	1525	0	0	0
T22	906	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	70047060	5611	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70047060	5611	0	0
T1	14289	14	0	0
T2	0	72	0	0
T3	0	20	0	0
T4	142537	0	0	0
T8	0	68	0	0
T9	0	73	0	0
T10	0	8	0	0
T11	0	11	0	0
T12	0	149	0	0
T13	0	32	0	0
T14	0	14	0	0
T15	1672	0	0	0
T16	2414	0	0	0
T17	968	0	0	0
T18	2929	0	0	0
T19	842	0	0	0
T20	1053	0	0	0
T21	1525	0	0	0
T22	906	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	70047060	7705	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70047060	7705	0	0
T1	14289	14	0	0
T2	0	98	0	0
T3	0	23	0	0
T4	142537	0	0	0
T8	0	107	0	0
T9	0	93	0	0
T10	0	12	0	0
T11	0	18	0	0
T12	0	228	0	0
T13	0	44	0	0
T14	0	22	0	0
T15	1672	0	0	0
T16	2414	0	0	0
T17	968	0	0	0
T18	2929	0	0	0
T19	842	0	0	0
T20	1053	0	0	0
T21	1525	0	0	0
T22	906	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	70047060	7684	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70047060	7684	0	0
T1	14289	14	0	0
T2	0	98	0	0
T3	0	22	0	0
T4	142537	0	0	0
T8	0	107	0	0
T9	0	93	0	0
T10	0	11	0	0
T11	0	19	0	0
T12	0	227	0	0
T13	0	44	0	0
T14	0	21	0	0
T15	1672	0	0	0
T16	2414	0	0	0
T17	968	0	0	0
T18	2929	0	0	0
T19	842	0	0	0
T20	1053	0	0	0
T21	1525	0	0	0
T22	906	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	70047060	11449	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70047060	11449	0	0
T1	14289	17	0	0
T2	0	144	0	0
T3	0	28	0	0
T4	142537	0	0	0
T8	0	178	0	0
T9	0	127	0	0
T10	0	18	0	0
T11	0	28	0	0
T12	0	377	0	0
T13	0	72	0	0
T14	0	36	0	0
T15	1672	0	0	0
T16	2414	0	0	0
T17	968	0	0	0
T18	2929	0	0	0
T19	842	0	0	0
T20	1053	0	0	0
T21	1525	0	0	0
T22	906	0	0	0