Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T1
0	1	Unreachable
1	0	Covered	T2,T25,T3

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	70047060	68263105	0	0
AllClkBypReqTrue_A	70047060	80096	0	0
IoClkBypReqFalse_A	70047060	68210583	0	2310
IoClkBypReqTrue_A	70047060	128318	0	0
LcClkBypAckFalse_A	70047060	68268968	0	0
LcClkBypAckTrue_A	70047060	74233	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70047060	68263105	0	0
T1	14289	14268	0	0
T4	142537	142385	0	0
T5	1504	1443	0	0
T6	2531	2429	0	0
T15	1672	1488	0	0
T16	2414	2320	0	0
T17	968	818	0	0
T18	2929	2899	0	0
T19	842	818	0	0
T20	1053	1041	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70047060	80096	0	0
T2	405780	604	0	0
T9	0	286	0	0
T17	968	34	0	0
T18	2929	0	0	0
T19	842	0	0	0
T20	1053	0	0	0
T21	1525	55	0	0
T22	906	97	0	0
T25	23946	27	0	0
T26	1472	0	0	0
T27	2005	339	0	0
T30	0	55	0	0
T31	0	206	0	0
T35	0	30	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70047060	68210583	0	2310
T1	14289	14266	0	3
T4	142537	142383	0	3
T5	1504	1441	0	3
T6	2531	2427	0	3
T15	1672	1486	0	3
T16	2414	2318	0	3
T17	968	801	0	3
T18	2929	2897	0	3
T19	842	816	0	3
T20	1053	933	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70047060	128318	0	0
T2	405780	1049	0	0
T17	968	49	0	0
T18	2929	0	0	0
T19	842	0	0	0
T20	1053	106	0	0
T21	1525	0	0	0
T22	906	72	0	0
T25	23946	71	0	0
T26	1472	0	0	0
T27	2005	541	0	0
T30	0	123	0	0
T31	0	28	0	0
T35	0	90	0	0
T123	0	644	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70047060	68268968	0	0
T1	14289	14268	0	0
T4	142537	142385	0	0
T5	1504	1443	0	0
T6	2531	2429	0	0
T15	1672	1488	0	0
T16	2414	2320	0	0
T17	968	806	0	0
T18	2929	2899	0	0
T19	842	818	0	0
T20	1053	996	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70047060	74233	0	0
T2	405780	516	0	0
T17	968	46	0	0
T18	2929	0	0	0
T19	842	0	0	0
T20	1053	45	0	0
T21	1525	0	0	0
T22	906	66	0	0
T25	23946	64	0	0
T26	1472	0	0	0
T27	2005	337	0	0
T30	0	111	0	0
T31	0	25	0	0
T35	0	24	0	0
T123	0	162	0	0