Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	989804736	9330	0	0
TransStop_A	989804736	4915	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	989804736	9330	0	0
T1	571588	0	0	0
T2	0	82	0	0
T3	0	56	0	0
T4	533780	0	0	0
T5	22288	16	0	0
T6	21092	37	0	0
T9	0	112	0	0
T15	6692	0	0	0
T16	10064	30	0	0
T17	8064	0	0	0
T18	43396	36	0	0
T19	13816	0	0	0
T20	84320	0	0	0
T32	0	3	0	0
T124	0	4	0	0
T125	0	4	0	0
T126	0	14	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	989804736	4915	0	0
T1	571588	0	0	0
T2	0	41	0	0
T3	0	28	0	0
T4	533780	0	0	0
T5	22288	9	0	0
T6	21092	31	0	0
T9	0	55	0	0
T15	6692	0	0	0
T16	10064	16	0	0
T17	8064	0	0	0
T18	43396	11	0	0
T19	13816	0	0	0
T20	84320	0	0	0
T32	0	3	0	0
T124	0	4	0	0
T125	0	4	0	0
T126	0	9	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	247451184	2382	0	0
TransStop_A	247451184	1270	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247451184	2382	0	0
T1	142897	0	0	0
T2	0	22	0	0
T3	0	16	0	0
T4	133445	0	0	0
T5	5572	5	0	0
T6	5273	13	0	0
T9	0	33	0	0
T15	1673	0	0	0
T16	2516	8	0	0
T17	2016	0	0	0
T18	10849	10	0	0
T19	3454	0	0	0
T20	21080	0	0	0
T32	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247451184	1270	0	0
T1	142897	0	0	0
T2	0	12	0	0
T3	0	8	0	0
T4	133445	0	0	0
T5	5572	3	0	0
T6	5273	11	0	0
T9	0	18	0	0
T15	1673	0	0	0
T16	2516	5	0	0
T17	2016	0	0	0
T18	10849	4	0	0
T19	3454	0	0	0
T20	21080	0	0	0
T32	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	247451184	2302	0	0
TransStop_A	247451184	1201	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247451184	2302	0	0
T1	142897	0	0	0
T2	0	19	0	0
T3	0	13	0	0
T4	133445	0	0	0
T5	5572	4	0	0
T6	5273	11	0	0
T9	0	26	0	0
T15	1673	0	0	0
T16	2516	7	0	0
T17	2016	0	0	0
T18	10849	7	0	0
T19	3454	0	0	0
T20	21080	0	0	0
T32	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247451184	1201	0	0
T1	142897	0	0	0
T2	0	9	0	0
T3	0	6	0	0
T4	133445	0	0	0
T5	5572	2	0	0
T6	5273	8	0	0
T9	0	12	0	0
T15	1673	0	0	0
T16	2516	2	0	0
T17	2016	0	0	0
T18	10849	2	0	0
T19	3454	0	0	0
T20	21080	0	0	0
T32	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	247451184	2339	0	0
TransStop_A	247451184	1208	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247451184	2339	0	0
T1	142897	0	0	0
T2	0	22	0	0
T3	0	17	0	0
T4	133445	0	0	0
T5	5572	4	0	0
T6	5273	5	0	0
T9	0	24	0	0
T15	1673	0	0	0
T16	2516	7	0	0
T17	2016	0	0	0
T18	10849	10	0	0
T19	3454	0	0	0
T20	21080	0	0	0
T32	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247451184	1208	0	0
T1	142897	0	0	0
T2	0	10	0	0
T3	0	10	0	0
T4	133445	0	0	0
T5	5572	1	0	0
T6	5273	5	0	0
T9	0	13	0	0
T15	1673	0	0	0
T16	2516	5	0	0
T17	2016	0	0	0
T18	10849	3	0	0
T19	3454	0	0	0
T20	21080	0	0	0
T32	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	247451184	2307	0	0
TransStop_A	247451184	1236	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247451184	2307	0	0
T1	142897	0	0	0
T2	0	19	0	0
T3	0	10	0	0
T4	133445	0	0	0
T5	5572	3	0	0
T6	5273	8	0	0
T9	0	29	0	0
T15	1673	0	0	0
T16	2516	8	0	0
T17	2016	0	0	0
T18	10849	9	0	0
T19	3454	0	0	0
T20	21080	0	0	0
T124	0	1	0	0
T125	0	1	0	0
T126	0	14	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247451184	1236	0	0
T1	142897	0	0	0
T2	0	10	0	0
T3	0	4	0	0
T4	133445	0	0	0
T5	5572	3	0	0
T6	5273	7	0	0
T9	0	12	0	0
T15	1673	0	0	0
T16	2516	4	0	0
T17	2016	0	0	0
T18	10849	2	0	0
T19	3454	0	0	0
T20	21080	0	0	0
T124	0	1	0	0
T125	0	1	0	0
T126	0	9	0	0