Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	70047060	8208656	0	57

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70047060	8208656	0	57
T1	14289	3555	0	1
T2	0	43764	0	0
T3	0	7633	0	0
T4	142537	0	0	0
T8	0	58899	0	0
T9	0	30907	0	0
T10	0	6769	0	1
T11	0	12781	0	1
T12	0	362522	0	0
T14	0	0	0	1
T15	1672	0	0	0
T16	2414	0	0	0
T17	968	0	0	0
T18	2929	0	0	0
T19	842	0	0	0
T20	1053	0	0	0
T21	1525	0	0	0
T22	906	0	0	0
T23	0	875	0	1
T24	0	891	0	1
T127	0	0	0	1
T128	0	0	0	1
T129	0	0	0	1
T130	0	0	0	1