Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	70987422	1687619	0	0
clk_enables_rd_A	70987422	24740	0	0
clk_hints_rd_A	70987422	21750	0	0
extclk_ctrl_rd_A	70987422	27582	0	0
extclk_ctrl_regwen_rd_A	70987422	20561	0	0
jitter_enable_rd_A	70987422	27150	0	0
jitter_regwen_rd_A	70987422	21582	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70987422	1687619	0	0
T12	214487	105420	0	0
T13	125432	0	0	0
T34	0	55206	0	0
T41	0	164012	0	0
T44	0	160002	0	0
T68	0	129815	0	0
T69	0	169702	0	0
T70	0	43591	0	0
T71	0	178780	0	0
T72	0	65254	0	0
T73	0	182888	0	0
T74	760	0	0	0
T75	1125	0	0	0
T76	1870	0	0	0
T77	1549	0	0	0
T78	1621	0	0	0
T79	1121	0	0	0
T80	220628	0	0	0
T81	1202	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70987422	24740	0	0
T2	405780	2	0	0
T3	0	3	0	0
T25	23946	0	0	0
T26	1472	0	0	0
T27	2005	0	0	0
T28	1370	0	0	0
T29	1945	0	0	0
T30	1650	0	0	0
T31	2312	0	0	0
T32	803	0	0	0
T34	0	2253	0	0
T35	856	0	0	0
T130	0	12	0	0
T150	0	7	0	0
T151	0	8	0	0
T152	0	6	0	0
T153	0	1	0	0
T154	0	13	0	0
T155	0	3	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70987422	21750	0	0
T2	405780	6	0	0
T3	0	9	0	0
T25	23946	0	0	0
T26	1472	0	0	0
T27	2005	0	0	0
T28	1370	0	0	0
T29	1945	0	0	0
T30	1650	0	0	0
T31	2312	0	0	0
T32	803	0	0	0
T34	0	1843	0	0
T35	856	0	0	0
T130	0	10	0	0
T150	0	3	0	0
T151	0	6	0	0
T152	0	3	0	0
T153	0	5	0	0
T154	0	10	0	0
T156	0	6	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70987422	27582	0	0
T2	405780	126	0	0
T21	1525	6	0	0
T22	906	0	0	0
T25	23946	0	0	0
T26	1472	0	0	0
T27	2005	59	0	0
T28	1370	0	0	0
T29	1945	0	0	0
T30	1650	0	0	0
T31	2312	0	0	0
T36	0	127	0	0
T37	0	31	0	0
T123	0	63	0	0
T131	0	1	0	0
T157	0	14	0	0
T158	0	14	0	0
T159	0	87	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70987422	20561	0	0
T34	0	2025	0	0
T36	110415	54	0	0
T37	13553	11	0	0
T38	23555	47	0	0
T68	0	4617	0	0
T69	0	5669	0	0
T91	1513	0	0	0
T92	1270	0	0	0
T122	11456	0	0	0
T160	0	56	0	0
T161	0	3	0	0
T162	0	20	0	0
T163	0	1	0	0
T164	1627	0	0	0
T165	2198	0	0	0
T166	1367	0	0	0
T167	1171	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70987422	27150	0	0
T2	405780	203	0	0
T3	0	84	0	0
T25	23946	0	0	0
T26	1472	0	0	0
T27	2005	0	0	0
T28	1370	0	0	0
T29	1945	0	0	0
T30	1650	0	0	0
T31	2312	0	0	0
T32	803	0	0	0
T34	0	2573	0	0
T35	856	0	0	0
T130	0	283	0	0
T150	0	116	0	0
T151	0	451	0	0
T152	0	92	0	0
T153	0	98	0	0
T156	0	111	0	0
T168	0	72	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70987422	21582	0	0
T34	198972	2259	0	0
T58	0	9	0	0
T65	0	35	0	0
T68	0	4897	0	0
T69	0	6079	0	0
T70	0	839	0	0
T84	0	53	0	0
T127	47056	0	0	0
T128	17946	0	0	0
T129	25512	0	0	0
T150	1984	0	0	0
T151	92795	0	0	0
T169	0	2305	0	0
T170	0	2859	0	0
T171	0	3	0	0
T172	1642	0	0	0
T173	1632	0	0	0
T174	1558	0	0	0
T175	1544	0	0	0