Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	210141180	361	0	0
StatusRise_A	210141180	361	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210141180	361	0	0
T2	811560	0	0	0
T3	278615	0	0	0
T19	1684	2	0	0
T20	2106	0	0	0
T21	3050	0	0	0
T22	1812	0	0	0
T25	47892	0	0	0
T26	2944	0	0	0
T27	4010	0	0	0
T28	4110	2	0	0
T29	5835	20	0	0
T30	1650	0	0	0
T31	2312	0	0	0
T32	803	0	0	0
T33	57248	0	0	0
T35	856	0	0	0
T43	0	8	0	0
T51	0	8	0	0
T53	0	10	0	0
T98	0	7	0	0
T123	3068	0	0	0
T166	0	9	0	0
T174	0	5	0	0
T176	0	8	0	0
T177	0	2	0	0
T178	1338	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210141180	361	0	0
T2	811560	0	0	0
T3	278615	0	0	0
T19	1684	2	0	0
T20	2106	0	0	0
T21	3050	0	0	0
T22	1812	0	0	0
T25	47892	0	0	0
T26	2944	0	0	0
T27	4010	0	0	0
T28	4110	2	0	0
T29	5835	20	0	0
T30	1650	0	0	0
T31	2312	0	0	0
T32	803	0	0	0
T33	57248	0	0	0
T35	856	0	0	0
T43	0	8	0	0
T51	0	8	0	0
T53	0	10	0	0
T98	0	7	0	0
T123	3068	0	0	0
T166	0	9	0	0
T174	0	5	0	0
T176	0	8	0	0
T177	0	2	0	0
T178	1338	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	70047060	117	0	0
StatusRise_A	70047060	117	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70047060	117	0	0
T2	405780	0	0	0
T19	842	1	0	0
T20	1053	0	0	0
T21	1525	0	0	0
T22	906	0	0	0
T25	23946	0	0	0
T26	1472	0	0	0
T27	2005	0	0	0
T28	1370	0	0	0
T29	1945	5	0	0
T43	0	3	0	0
T51	0	2	0	0
T53	0	3	0	0
T98	0	2	0	0
T166	0	4	0	0
T174	0	1	0	0
T176	0	2	0	0
T177	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70047060	117	0	0
T2	405780	0	0	0
T19	842	1	0	0
T20	1053	0	0	0
T21	1525	0	0	0
T22	906	0	0	0
T25	23946	0	0	0
T26	1472	0	0	0
T27	2005	0	0	0
T28	1370	0	0	0
T29	1945	5	0	0
T43	0	3	0	0
T51	0	2	0	0
T53	0	3	0	0
T98	0	2	0	0
T166	0	4	0	0
T174	0	1	0	0
T176	0	2	0	0
T177	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	70047060	127	0	0
StatusRise_A	70047060	127	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70047060	127	0	0
T2	405780	0	0	0
T19	842	1	0	0
T20	1053	0	0	0
T21	1525	0	0	0
T22	906	0	0	0
T25	23946	0	0	0
T26	1472	0	0	0
T27	2005	0	0	0
T28	1370	1	0	0
T29	1945	8	0	0
T43	0	3	0	0
T51	0	3	0	0
T53	0	4	0	0
T98	0	3	0	0
T166	0	3	0	0
T174	0	2	0	0
T176	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70047060	127	0	0
T2	405780	0	0	0
T19	842	1	0	0
T20	1053	0	0	0
T21	1525	0	0	0
T22	906	0	0	0
T25	23946	0	0	0
T26	1472	0	0	0
T27	2005	0	0	0
T28	1370	1	0	0
T29	1945	8	0	0
T43	0	3	0	0
T51	0	3	0	0
T53	0	4	0	0
T98	0	3	0	0
T166	0	3	0	0
T174	0	2	0	0
T176	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	70047060	117	0	0
StatusRise_A	70047060	117	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70047060	117	0	0
T3	278615	0	0	0
T28	1370	1	0	0
T29	1945	7	0	0
T30	1650	0	0	0
T31	2312	0	0	0
T32	803	0	0	0
T33	57248	0	0	0
T35	856	0	0	0
T43	0	2	0	0
T51	0	3	0	0
T53	0	3	0	0
T98	0	2	0	0
T123	3068	0	0	0
T166	0	2	0	0
T174	0	2	0	0
T176	0	4	0	0
T177	0	1	0	0
T178	1338	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70047060	117	0	0
T3	278615	0	0	0
T28	1370	1	0	0
T29	1945	7	0	0
T30	1650	0	0	0
T31	2312	0	0	0
T32	803	0	0	0
T33	57248	0	0	0
T35	856	0	0	0
T43	0	2	0	0
T51	0	3	0	0
T53	0	3	0	0
T98	0	2	0	0
T123	3068	0	0	0
T166	0	2	0	0
T174	0	2	0	0
T176	0	4	0	0
T177	0	1	0	0
T178	1338	0	0	0