Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T2,T25
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	30881	0	0
CgEnOn_A	2147483647	22279	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	30881	0	0
T1	811582	3	0	0
T2	3207187	22	0	0
T4	707489	3	0	0
T5	31587	8	0	0
T6	29860	16	0	0
T15	9419	3	0	0
T16	14266	11	0	0
T17	11437	3	0	0
T18	61572	13	0	0
T19	33874	12	0	0
T20	209146	3	0	0
T21	6433	0	0	0
T22	27623	0	0	0
T25	182350	0	0	0
T26	6181	0	0	0
T27	35177	0	0	0
T28	7168	5	0	0
T29	7876	45	0	0
T30	808	0	0	0
T31	1121	0	0	0
T32	838	1	0	0
T43	0	15	0	0
T51	0	15	0	0
T53	0	20	0	0
T98	0	15	0	0
T166	0	15	0	0
T174	0	10	0	0
T176	0	10	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	22279	0	0
T1	571584	0	0	0
T2	4488008	104	0	0
T3	0	100	0	0
T4	533776	0	0	0
T5	22288	5	0	0
T6	21092	13	0	0
T9	0	48	0	0
T15	6688	0	0	0
T16	10060	8	0	0
T17	8060	0	0	0
T18	43396	10	0	0
T19	33874	9	0	0
T20	209146	0	0	0
T21	9024	0	0	0
T22	38910	0	0	0
T25	241426	0	0	0
T26	8664	11	0	0
T27	49738	0	0	0
T28	9730	8	0	0
T29	10763	69	0	0
T30	808	0	0	0
T31	1121	0	0	0
T32	838	1	0	0
T43	0	24	0	0
T51	0	15	0	0
T53	0	20	0	0
T98	0	15	0	0
T124	0	3	0	0
T166	0	15	0	0
T174	0	10	0	0
T176	0	10	0	0
T178	0	12	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T2,T25
1	0	Unreachable
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	115428507	131	0	0
CgEnOn_A	115428507	131	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115428507	131	0	0
T2	366146	0	0	0
T19	1627	1	0	0
T20	10550	0	0	0
T21	732	0	0	0
T22	3379	0	0	0
T25	16848	0	0	0
T26	695	0	0	0
T27	4574	0	0	0
T28	709	1	0	0
T29	798	8	0	0
T43	0	3	0	0
T51	0	3	0	0
T53	0	4	0	0
T98	0	3	0	0
T166	0	3	0	0
T174	0	2	0	0
T176	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115428507	131	0	0
T2	366146	0	0	0
T19	1627	1	0	0
T20	10550	0	0	0
T21	732	0	0	0
T22	3379	0	0	0
T25	16848	0	0	0
T26	695	0	0	0
T27	4574	0	0	0
T28	709	1	0	0
T29	798	8	0	0
T43	0	3	0	0
T51	0	3	0	0
T53	0	4	0	0
T98	0	3	0	0
T166	0	3	0	0
T174	0	2	0	0
T176	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T2,T25
1	0	Unreachable
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	57713844	131	0	0
CgEnOn_A	57713844	131	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57713844	131	0	0
T2	183069	0	0	0
T19	814	1	0	0
T20	5275	0	0	0
T21	366	0	0	0
T22	1690	0	0	0
T25	8424	0	0	0
T26	347	0	0	0
T27	2284	0	0	0
T28	355	1	0	0
T29	399	8	0	0
T43	0	3	0	0
T51	0	3	0	0
T53	0	4	0	0
T98	0	3	0	0
T166	0	3	0	0
T174	0	2	0	0
T176	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57713844	131	0	0
T2	183069	0	0	0
T19	814	1	0	0
T20	5275	0	0	0
T21	366	0	0	0
T22	1690	0	0	0
T25	8424	0	0	0
T26	347	0	0	0
T27	2284	0	0	0
T28	355	1	0	0
T29	399	8	0	0
T43	0	3	0	0
T51	0	3	0	0
T53	0	4	0	0
T98	0	3	0	0
T166	0	3	0	0
T174	0	2	0	0
T176	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T2,T25
1	0	Unreachable
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	57713844	131	0	0
CgEnOn_A	57713844	131	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57713844	131	0	0
T2	183069	0	0	0
T19	814	1	0	0
T20	5275	0	0	0
T21	366	0	0	0
T22	1690	0	0	0
T25	8424	0	0	0
T26	347	0	0	0
T27	2284	0	0	0
T28	355	1	0	0
T29	399	8	0	0
T43	0	3	0	0
T51	0	3	0	0
T53	0	4	0	0
T98	0	3	0	0
T166	0	3	0	0
T174	0	2	0	0
T176	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57713844	131	0	0
T2	183069	0	0	0
T19	814	1	0	0
T20	5275	0	0	0
T21	366	0	0	0
T22	1690	0	0	0
T25	8424	0	0	0
T26	347	0	0	0
T27	2284	0	0	0
T28	355	1	0	0
T29	399	8	0	0
T43	0	3	0	0
T51	0	3	0	0
T53	0	4	0	0
T98	0	3	0	0
T166	0	3	0	0
T174	0	2	0	0
T176	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T2,T25
1	0	Unreachable
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	57713844	131	0	0
CgEnOn_A	57713844	131	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57713844	131	0	0
T2	183069	0	0	0
T19	814	1	0	0
T20	5275	0	0	0
T21	366	0	0	0
T22	1690	0	0	0
T25	8424	0	0	0
T26	347	0	0	0
T27	2284	0	0	0
T28	355	1	0	0
T29	399	8	0	0
T43	0	3	0	0
T51	0	3	0	0
T53	0	4	0	0
T98	0	3	0	0
T166	0	3	0	0
T174	0	2	0	0
T176	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57713844	131	0	0
T2	183069	0	0	0
T19	814	1	0	0
T20	5275	0	0	0
T21	366	0	0	0
T22	1690	0	0	0
T25	8424	0	0	0
T26	347	0	0	0
T27	2284	0	0	0
T28	355	1	0	0
T29	399	8	0	0
T43	0	3	0	0
T51	0	3	0	0
T53	0	4	0	0
T98	0	3	0	0
T166	0	3	0	0
T174	0	2	0	0
T176	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T2,T25
1	0	Unreachable
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	232233566	131	0	0
CgEnOn_A	232233566	127	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232233566	131	0	0
T2	731606	0	0	0
T19	3320	1	0	0
T20	20236	0	0	0
T21	1493	0	0	0
T22	6218	0	0	0
T25	33804	0	0	0
T26	1441	0	0	0
T27	7703	0	0	0
T28	1498	1	0	0
T29	1690	8	0	0
T43	0	3	0	0
T51	0	3	0	0
T53	0	4	0	0
T98	0	3	0	0
T166	0	3	0	0
T174	0	2	0	0
T176	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232233566	127	0	0
T2	731606	0	0	0
T19	3320	1	0	0
T20	20236	0	0	0
T21	1493	0	0	0
T22	6218	0	0	0
T25	33804	0	0	0
T26	1441	0	0	0
T27	7703	0	0	0
T28	1498	1	0	0
T29	1690	8	0	0
T43	0	3	0	0
T51	0	3	0	0
T53	0	4	0	0
T98	0	3	0	0
T166	0	3	0	0
T174	0	2	0	0
T176	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T2,T25
1	0	Unreachable
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	247450758	118	0	0
CgEnOn_A	247450758	117	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247450758	118	0	0
T2	780114	0	0	0
T19	3454	1	0	0
T20	21079	0	0	0
T21	1555	0	0	0
T22	6478	0	0	0
T25	53213	0	0	0
T26	1502	0	0	0
T27	8024	0	0	0
T28	1575	0	0	0
T29	1688	5	0	0
T43	0	3	0	0
T51	0	2	0	0
T53	0	3	0	0
T98	0	2	0	0
T166	0	4	0	0
T174	0	1	0	0
T176	0	2	0	0
T177	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247450758	117	0	0
T2	780114	0	0	0
T19	3454	1	0	0
T20	21079	0	0	0
T21	1555	0	0	0
T22	6478	0	0	0
T25	53213	0	0	0
T26	1502	0	0	0
T27	8024	0	0	0
T28	1575	0	0	0
T29	1688	5	0	0
T43	0	3	0	0
T51	0	2	0	0
T53	0	3	0	0
T98	0	2	0	0
T166	0	4	0	0
T174	0	1	0	0
T176	0	2	0	0
T177	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T2,T25
1	0	Unreachable
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	247450758	118	0	0
CgEnOn_A	247450758	117	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247450758	118	0	0
T2	780114	0	0	0
T19	3454	1	0	0
T20	21079	0	0	0
T21	1555	0	0	0
T22	6478	0	0	0
T25	53213	0	0	0
T26	1502	0	0	0
T27	8024	0	0	0
T28	1575	0	0	0
T29	1688	5	0	0
T43	0	3	0	0
T51	0	2	0	0
T53	0	3	0	0
T98	0	2	0	0
T166	0	4	0	0
T174	0	1	0	0
T176	0	2	0	0
T177	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247450758	117	0	0
T2	780114	0	0	0
T19	3454	1	0	0
T20	21079	0	0	0
T21	1555	0	0	0
T22	6478	0	0	0
T25	53213	0	0	0
T26	1502	0	0	0
T27	8024	0	0	0
T28	1575	0	0	0
T29	1688	5	0	0
T43	0	3	0	0
T51	0	2	0	0
T53	0	3	0	0
T98	0	2	0	0
T166	0	4	0	0
T174	0	1	0	0
T176	0	2	0	0
T177	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T25,T28
1	0	Unreachable
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	118822691	117	0	0
CgEnOn_A	118822691	117	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118822691	117	0	0
T3	974025	0	0	0
T28	746	1	0	0
T29	815	7	0	0
T30	808	0	0	0
T31	1121	0	0	0
T32	838	0	0	0
T33	95517	0	0	0
T35	1713	0	0	0
T43	0	2	0	0
T51	0	3	0	0
T53	0	3	0	0
T98	0	2	0	0
T123	1487	0	0	0
T166	0	2	0	0
T174	0	2	0	0
T176	0	4	0	0
T177	0	1	0	0
T178	662	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118822691	117	0	0
T3	974025	0	0	0
T28	746	1	0	0
T29	815	7	0	0
T30	808	0	0	0
T31	1121	0	0	0
T32	838	0	0	0
T33	95517	0	0	0
T35	1713	0	0	0
T43	0	2	0	0
T51	0	3	0	0
T53	0	3	0	0
T98	0	2	0	0
T123	1487	0	0	0
T166	0	2	0	0
T174	0	2	0	0
T176	0	4	0	0
T177	0	1	0	0
T178	662	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T28,T29
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	57713844	5010	0	0
CgEnOn_A	57713844	2864	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57713844	5010	0	0
T1	34274	1	0	0
T4	24803	1	0	0
T5	1317	1	0	0
T6	1235	1	0	0
T15	375	1	0	0
T16	597	1	0	0
T17	481	1	0	0
T18	2587	1	0	0
T19	814	2	0	0
T20	5275	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57713844	2864	0	0
T2	183069	26	0	0
T3	0	27	0	0
T9	0	5	0	0
T19	814	1	0	0
T20	5275	0	0	0
T21	366	0	0	0
T22	1690	0	0	0
T25	8424	0	0	0
T26	347	4	0	0
T27	2284	0	0	0
T28	355	1	0	0
T29	399	8	0	0
T43	0	3	0	0
T124	0	1	0	0
T178	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T28,T29
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	115428507	5029	0	0
CgEnOn_A	115428507	2883	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115428507	5029	0	0
T1	68548	1	0	0
T4	49606	1	0	0
T5	2634	1	0	0
T6	2471	1	0	0
T15	750	1	0	0
T16	1195	1	0	0
T17	961	1	0	0
T18	5174	1	0	0
T19	1627	2	0	0
T20	10550	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115428507	2883	0	0
T2	366146	26	0	0
T3	0	29	0	0
T9	0	5	0	0
T19	1627	1	0	0
T20	10550	0	0	0
T21	732	0	0	0
T22	3379	0	0	0
T25	16848	0	0	0
T26	695	3	0	0
T27	4574	0	0	0
T28	709	1	0	0
T29	798	8	0	0
T43	0	3	0	0
T124	0	1	0	0
T178	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T28,T29
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	232233566	5034	0	0
CgEnOn_A	232233566	2884	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232233566	5034	0	0
T1	137176	1	0	0
T4	99304	1	0	0
T5	5348	1	0	0
T6	5062	1	0	0
T15	1606	1	0	0
T16	2414	1	0	0
T17	1935	1	0	0
T18	10415	1	0	0
T19	3320	2	0	0
T20	20236	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232233566	2884	0	0
T2	731606	30	0	0
T3	0	28	0	0
T9	0	5	0	0
T19	3320	1	0	0
T20	20236	0	0	0
T21	1493	0	0	0
T22	6218	0	0	0
T25	33804	0	0	0
T26	1441	4	0	0
T27	7703	0	0	0
T28	1498	1	0	0
T29	1690	8	0	0
T43	0	3	0	0
T124	0	1	0	0
T178	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T29,T43
1	0	Covered	T5,T6,T1
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	118822691	4998	0	0
CgEnOn_A	118822691	2848	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118822691	4998	0	0
T1	68591	1	0	0
T4	69814	1	0	0
T5	2674	1	0	0
T6	2531	1	0	0
T15	803	1	0	0
T16	1208	1	0	0
T17	968	1	0	0
T18	5208	1	0	0
T19	1686	1	0	0
T20	10118	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118822691	2848	0	0
T2	385981	27	0	0
T3	0	26	0	0
T9	0	5	0	0
T25	25542	0	0	0
T26	721	4	0	0
T27	3851	0	0	0
T28	746	1	0	0
T29	815	7	0	0
T30	808	0	0	0
T31	1121	0	0	0
T32	838	0	0	0
T35	1713	0	0	0
T43	0	2	0	0
T82	0	1	0	0
T124	0	1	0	0
T178	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T2,T25
1	0	Covered	T5,T6,T16
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	247450758	2500	0	0
CgEnOn_A	247450758	2499	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247450758	2500	0	0
T1	142896	0	0	0
T2	0	22	0	0
T3	0	16	0	0
T4	133444	0	0	0
T5	5572	5	0	0
T6	5273	13	0	0
T9	0	33	0	0
T15	1672	0	0	0
T16	2515	8	0	0
T17	2015	0	0	0
T18	10849	10	0	0
T19	3454	1	0	0
T20	21079	0	0	0
T29	0	5	0	0
T32	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247450758	2499	0	0
T1	142896	0	0	0
T2	0	22	0	0
T3	0	16	0	0
T4	133444	0	0	0
T5	5572	5	0	0
T6	5273	13	0	0
T9	0	33	0	0
T15	1672	0	0	0
T16	2515	8	0	0
T17	2015	0	0	0
T18	10849	10	0	0
T19	3454	1	0	0
T20	21079	0	0	0
T29	0	5	0	0
T32	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T2,T25
1	0	Covered	T5,T6,T16
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	247450758	2420	0	0
CgEnOn_A	247450758	2419	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247450758	2420	0	0
T1	142896	0	0	0
T2	0	19	0	0
T3	0	13	0	0
T4	133444	0	0	0
T5	5572	4	0	0
T6	5273	11	0	0
T9	0	26	0	0
T15	1672	0	0	0
T16	2515	7	0	0
T17	2015	0	0	0
T18	10849	7	0	0
T19	3454	1	0	0
T20	21079	0	0	0
T29	0	5	0	0
T32	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247450758	2419	0	0
T1	142896	0	0	0
T2	0	19	0	0
T3	0	13	0	0
T4	133444	0	0	0
T5	5572	4	0	0
T6	5273	11	0	0
T9	0	26	0	0
T15	1672	0	0	0
T16	2515	7	0	0
T17	2015	0	0	0
T18	10849	7	0	0
T19	3454	1	0	0
T20	21079	0	0	0
T29	0	5	0	0
T32	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T2,T25
1	0	Covered	T5,T6,T16
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	247450758	2457	0	0
CgEnOn_A	247450758	2456	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247450758	2457	0	0
T1	142896	0	0	0
T2	0	22	0	0
T3	0	17	0	0
T4	133444	0	0	0
T5	5572	4	0	0
T6	5273	5	0	0
T9	0	24	0	0
T15	1672	0	0	0
T16	2515	7	0	0
T17	2015	0	0	0
T18	10849	10	0	0
T19	3454	1	0	0
T20	21079	0	0	0
T29	0	5	0	0
T32	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247450758	2456	0	0
T1	142896	0	0	0
T2	0	22	0	0
T3	0	17	0	0
T4	133444	0	0	0
T5	5572	4	0	0
T6	5273	5	0	0
T9	0	24	0	0
T15	1672	0	0	0
T16	2515	7	0	0
T17	2015	0	0	0
T18	10849	10	0	0
T19	3454	1	0	0
T20	21079	0	0	0
T29	0	5	0	0
T32	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T2,T25
1	0	Covered	T5,T6,T16
1	1	Covered	T5,T6,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	247450758	2425	0	0
CgEnOn_A	247450758	2424	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247450758	2425	0	0
T1	142896	0	0	0
T2	0	19	0	0
T3	0	10	0	0
T4	133444	0	0	0
T5	5572	3	0	0
T6	5273	8	0	0
T9	0	29	0	0
T15	1672	0	0	0
T16	2515	8	0	0
T17	2015	0	0	0
T18	10849	9	0	0
T19	3454	1	0	0
T20	21079	0	0	0
T29	0	5	0	0
T43	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	247450758	2424	0	0
T1	142896	0	0	0
T2	0	19	0	0
T3	0	10	0	0
T4	133444	0	0	0
T5	5572	3	0	0
T6	5273	8	0	0
T9	0	29	0	0
T15	1672	0	0	0
T16	2515	8	0	0
T17	2015	0	0	0
T18	10849	9	0	0
T19	3454	1	0	0
T20	21079	0	0	0
T29	0	5	0	0
T43	0	3	0	0